Patents by Inventor Toshiya Kotani

Toshiya Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9977855
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 22, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Fumiharu Nakajima, Hirotaka Ichikawa
  • Patent number: 9953126
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Fumiharu Nakajima, Hirotaka Ichikawa
  • Patent number: 9917049
    Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: March 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Fumiharu Nakajima, Toshiya Kotani, Hiromitsu Mashita, Takafumi Taguchi, Ryota Aburada, Chikaaki Kodama
  • Patent number: 9698157
    Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kono, Takaki Hashimoto, Yuji Setta, Toshiya Kotani, Chikaaki Kodama
  • Patent number: 9576100
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 21, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiro Miyoshi, Taiki Kimura, Hiromitsu Mashita, Fumiharu Nakajima, Tetsuaki Matsunawa, Toshiya Kotani, Chikaaki Kodama
  • Publication number: 20160343658
    Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
    Type: Application
    Filed: August 2, 2016
    Publication date: November 24, 2016
    Inventors: Fumiharu NAKAJIMA, Toshiya KOTANI, Hiromitsu MASHITA, Takafumi TAGUCHI, Ryota ABURADA, Chikaaki KODAMA
  • Publication number: 20160268278
    Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.
    Type: Application
    Filed: August 25, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuko KONO, Takaki Hashimoto, Yuji Setta, Toshiya Kotani, Chikaaki Kodama
  • Patent number: 9268208
    Abstract: One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: February 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Aburada, Hiromitsu Mashita, Taiga Uno, Masahiro Miyairi, Toshiya Kotani
  • Publication number: 20160026079
    Abstract: A mask pattern correcting method according to an embodiment is a correcting method of a mask pattern to be used in a semiconductor device manufacturing process. In the correcting method, a plurality of kernels calculated based on an optical system of an exposure tool is prepared. Weight coefficients for weighting the kernels, respectively, to be used when the kernels are synthesized, are calculated. The kernels are synthesized using the calculated weight coefficients. The mask pattern is corrected using the synthesized kernels.
    Type: Application
    Filed: January 29, 2015
    Publication date: January 28, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taiki KIMURA, Toshiya Kotani, Masanori Takahashi
  • Publication number: 20160013097
    Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
    Type: Application
    Filed: September 18, 2015
    Publication date: January 14, 2016
    Inventors: Fumiharu NAKAJIMA, Toshiya KOTANI, Hiromitsu MASHITA, Takafumi TAGUCHI, Ryota ABURADA, Chikaaki KODAMA
  • Patent number: 9207531
    Abstract: According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroko Nakamura, Koji Asakawa, Shigeki Hattori, Satoshi Tanaka, Toshiya Kotani
  • Patent number: 9177854
    Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: November 3, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Fumiharu Nakajima, Toshiya Kotani, Hiromitsu Mashita, Takafumi Taguchi, Ryota Aburada, Chikaaki Kodama
  • Publication number: 20150263026
    Abstract: According to one embodiment, a semiconductor device includes: a substrate including silicon; and a first element provided on the substrate and extending in a thickness direction of the substrate, a center position of an end face on the substrate side of the first element and a center position of an end face on an opposite side of the substrate side of the first element being different in a direction parallel to a major surface of the substrate.
    Type: Application
    Filed: July 25, 2014
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuko KONO, Ai Inoue, Toshiya Kotani, Chikaaki Kodama, Yasunobu Kai, Sadatoshi Murakami
  • Patent number: 9086634
    Abstract: According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kono, Kazuyuki Masukawa, Toshiya Kotani, Chikaaki Kodama, Yasunobu Kai
  • Publication number: 20150113485
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Seiro MIYOSHI, Taiki KIMURA, Hiromitsu MASHITA, Fumiharu NAKAJIMA, Tetsuaki MATSUNAWA, Toshiya KOTANI, Chikaaki KODAMA
  • Patent number: 8984454
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiro Miyoshi, Taiki Kimura, Hiromitsu Mashita, Fumiharu Nakajima, Tetsuaki Matsunawa, Toshiya Kotani, Chikaaki Kodama
  • Publication number: 20150021782
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 22, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chikaaki KODAMA, Koichi NAKAYAMA, Toshiya KOTANI, Shigeki NOJIMA, Fumiharu NAKAJIMA, Hirotaka ICHIKAWA
  • Publication number: 20150008584
    Abstract: According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventors: Takaki Hashimoto, Yasunobu Kai, Toshiya Kotani
  • Patent number: 8865589
    Abstract: According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaki Hashimoto, Yasunobu Kai, Toshiya Kotani
  • Patent number: RE46100
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota Aburada, Hiromitsu Mashita, Toshiya Kotani, Chikaaki Kodama