Patents by Inventor Toshiya Nakano

Toshiya Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190333414
    Abstract: A medical simulator has a human body model that simulates a human-body external shape at least from a head to a neck, an oral cavity portion, a nasal cavity portion, a pharynx portion, a larynx portion, a trachea portion, and an esophagus portion, thereby enabling at least training of an intubation procedure to be done. The medical simulator includes: a neck supporting portion that serves as a framework of the neck of the human body model and is provided so as to extend to the head; and a simulated thyroid cartilage portion that is connected by a first spring member to the neck supporting portion and is disposed in the larynx portion of the human body model.
    Type: Application
    Filed: August 2, 2017
    Publication date: October 31, 2019
    Inventors: Toshiya NAKANO, Masaki SHIMIZU, Yasuaki HIYAMA, Masaaki MATSUOKA, Hiroshige NAKAMURA, Hiromi TAKEUCHI, Yoshimi INAGAKI
  • Patent number: 9507966
    Abstract: According to one embodiment, a firmware stored in a ROM in an information processing device connects the information processing device to a first server through a network, and downloads a client program into a volatile memory in the information processing device from the first server. Also, the firmware launches the client program to connect the information processing device and a second server through the network, and turns off the power of the information processing device to erase content in the volatile memory, when the information processing device is disconnected from the network after connection between the information processing device and the second server is established.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: November 29, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiya Nakano, Yoshio Matsuoka, Yoshihiro Kaneko, Hideaki Uzawa
  • Publication number: 20150379308
    Abstract: According to one embodiment, a firmware stored in a ROM in an information processing device connects the information processing device to a first server through a network, and downloads a client program into a volatile memory in the information processing device from the first server. Also, the firmware launches the client program to connect the information processing device and a second server through the network, and turns off the power of the information processing device to erase content in the volatile memory, when the information processing device is disconnected from the network after connection between the information processing device and the second server is established.
    Type: Application
    Filed: December 3, 2014
    Publication date: December 31, 2015
    Inventors: Toshiya Nakano, Yoshio Matsuoka, Yoshihiro Kaneko, Hideaki Uzawa
  • Publication number: 20150347504
    Abstract: According to one embodiment, an electronic apparatus includes a processing circuit. The processing circuit is configured to acquire screen image data representing a screen image of the electronic apparatus including a window displayed by execution of software, acquire log data including time and date when the screen image data is acquired and software data indicating the software, and store the screen image data associated with the log data in a storage.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 3, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiya NAKANO
  • Patent number: 6889286
    Abstract: For providing a storage control unit to be connected to a fiber channel, in which a new storage control unit is added onto the fiber channel network during on-line operation and succeeds control information of a logical unit from the storage control unit which has been existing before, so as to be in charge of a process request issued to that logical unit from a host computer thereafter, wherein a control memory being able to memorize the control information is provided in each of the storage control units 30 and 40, which information is necessary when succeeding or taking over the logical unit and is represented by such as construction information of a magnetic disk drive within a disk drive unit 20 and construction information of the logical unit, so on. The contents of the control memory within the storage control unit 30 is copied into the control memory of the storage control unit 40 when the new storage control unit 40 is added onto the fiber channel network.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: May 3, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Hino, Toshiya Nakano, Tetsuya Kishimoto, Hidehiko Iwasaki, Kenji Muraoka, Kenichi Takamoto
  • Publication number: 20020184439
    Abstract: For providing a storage control unit to be connected to a fiber channel, in which a new storage control unit is added onto the fiber channel network during on-line operation and succeeds control information of a logical unit from the storage control unit which has been existing before, so as to be in charge of a process request issued to that logical unit from a host computer thereafter, wherein a control memory being able to memorize the control information is provided in each of the storage control units 30 and 40, which information is necessary when succeeding or taking over the logical unit and is represented by such as construction information of a magnetic disk drive within a disk drive unit 20 and construction information of the logical unit, so on. The contents of the control memory within the storage control unit 30 is copied into the control memory of the storage control unit 40 when the new storage control unit 40 is added onto the fiber channel network.
    Type: Application
    Filed: July 10, 2002
    Publication date: December 5, 2002
    Inventors: Naoki Hino, Toshiya Nakano, Tetsuya Kishimoto, Hidehiko Iwasaki, Kenji Muraoka, Kenichi Takamoto
  • Patent number: 6480934
    Abstract: For providing a storage control unit to be connected to a fiber channel, in which a new storage control unit is added onto the fiber channel network during on-line operation and succeeds control information of a logical unit from the storage control unit which has been existing before, so as to be in charge of a process request issued to that logical unit from a host computer thereafter, wherein a control memory being able to memorize the control information is provided in each of the storage control units 30 and 40, which information is necessary when succeeding or taking over the logical unit and is represented by such as construction information of a magnetic disk drive within a disk drive unit 20 and construction information of the logical unit, so on. The contents of the control memory within the storage control unit 30 is copied into the control memory of the storage control unit 40 when the new storage control unit 40 is added onto the fiber channel network.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: November 12, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Hino, Toshiya Nakano, Tetsuya Kishimoto, Hidehiko Iwasaki, Kenji Muraoka, Kenichi Takamoto
  • Patent number: 6396319
    Abstract: Disclosed is a semiconductor integrated circuit capable of performing a normal operation from immediately after turn-on of power without deteriorating degree of integration. The collector of an NPN bipolar transistor Q1 is connected to a terminal P1 and the emitter of the same is connected to a positive electrode of a reference voltage source 32. The emitter of an NPN bipolar transistor Q2 is connected to the terminal P1 and the collector of the same is connected to the positive pole of the reference voltage source 32. The reference voltage source 32 generates a reference voltage VREF2 from its positive electrode and the negative electrode is connected to the ground.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: May 28, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiya Nakano
  • Publication number: 20020014911
    Abstract: Disclosed is a semiconductor integrated circuit capable of performing a normal operation from immediately after turn-on of power without deteriorating degree of integration. The collector of an NPN bipolar transistor Q1 is connected to a terminal P1 and the emitter of the same is connected to a positive electrode of a reference voltage source 32. The emitter of an NPN bipolar transistor Q2 is connected to the terminal P1 and the collector of the same is connected to the positive pole of the reference voltage source 32. The reference voltage source 32 generates a reference voltage VREF2 from its positive electrode and the negative electrode is connected to the ground.
    Type: Application
    Filed: December 20, 2000
    Publication date: February 7, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Toshiya Nakano
  • Patent number: 6198315
    Abstract: A current detection circuit having a voltage conversion section for converting current flowing to a load to a voltage; an amplifier section having an operational amplifier for amplifying the voltage converted by the voltage conversion section; a constant current circuit section having a constant current circuit connected to an input of the operational amplifier; and a current detection section for detecting a load current from a voltage amplified by the amplifier section. The constant current circuit section shifts the input offset voltage to the operational amplifier of the amplifier section. As a result, a dead zone in which a load current cannot be detected due to the input offset voltage of the operational amplifier can be eliminated.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: March 6, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiya Nakano
  • Patent number: 6157202
    Abstract: A hybrid IC with a semiconductor power device and a control circuit for controlling the power device being bare-chip mounted on a substrate includes a wiring arranged between a power source line and a gate of the power device whereby the wiring connects the power source line to the gate during a burn-in test and is cut off after the burn-in test. The hybrid IC preferably provides a wiring pattern for disconnecting the control circuit to the gate of the power device during a burn-in test which is shortcircuited after the burn-in test.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: December 5, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiya Nakano
  • Patent number: 5675242
    Abstract: A semiconductor integrated circuit is disclosed in which a power MOSFET supplies a squib of automobile air bag systems with load current. The power MOSFET Q.sub.1 provides squib Z.sub.L with the load current, and load current signal which outputs from shunt resistor R.sub.s is provided an operational amplifier consisting of transistors Q.sub.4 -Q.sub.10 with a negative feedback signal, so that the load current to be supplied to the squib Z.sub.L is restricted. The negative feedback operation is interrupted by load current function interruption signal which inputs to terminal T.sub.6. A circuit which consists of two current mirror circuits composed of transistors Q.sub.4 -Q.sub.10 and constant current source I.sub.4 supplies the operational amplifier with constant current to interrupt the feedback operation.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: October 7, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiya Nakano
  • Patent number: 5672917
    Abstract: A semiconductor power switch system having a control portion and at least one semiconductor power switch unit (PSU) having a self-diagnosis function to simplify the connection lines between the control portion and the PSU. In the PSU, a diagnosing terminal for transmitting an abnormality signal is, by a connection line in the outer portion, connected to an input terminal for receiving a control signal so that the control signal from the control portion to the PSU and the abnormality signal from the PSU to the control portion are communicated through one bidirectional signal transmission line. That is, if an abnormality has taken place, a transistor is turned on so that the level of the bidirectional signal transmission line is fixed to the level of the abnormality signal through the diagnosing terminal and the connection line.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: September 30, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiya Nakano
  • Patent number: 5541544
    Abstract: A semiconductor integrated bipolar flip-flop circuit prevents or suppresses erroneous operation arising from a current induced by external noise and flowing through a parasitic capacitance associated with a p-type diffused resistor. The semiconductor integrated circuit includes bipolar transistors that are directly involved with set and reset operations of the flip-flop circuit having bases connected to a two-stage inverter including bipolar transistors so that the bases of the bipolar transistors involved in setting and resetting are not connected directly to a p-type diffused resistor.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: July 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiya Nakano
  • Patent number: 5483404
    Abstract: A semiconductor integrated circuit allows no through-current to flow to voltage-driven-type power control devices of an external circuit even when the grounding terminals are opened, thereby protecting the devices from breakdown.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: January 9, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiya Nakano
  • Patent number: 5459350
    Abstract: A resin sealed semiconductor device includes a current-detecting resistance for detecting current flowing in a semiconductor element that is a metallic resistance having a coefficient of thermal expansion almost equal to that of the lead frame. Compared to a conventional ceramic chip resistance, its coefficient of thermal expansion differs less from that of the lead frame, thereby preventing deterioration caused by heat stress.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: October 17, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shoji Date, Ziro Honda, Toshiya Nakano, Hazime Kato