Patents by Inventor Toshiya Uchida

Toshiya Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7158435
    Abstract: A fuse circuit has an actual fuse circuit block and a fuse monitor circuit. The actual fuse circuit block stores fuse information; on the other hand, the fuse monitor circuit monitors whether a supply voltage has reached an information capturable voltage at which the fuse information from the actual fuse circuit block can be correctly captured.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: January 2, 2007
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Kobayashi, Toshiya Uchida
  • Publication number: 20060273848
    Abstract: A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.
    Type: Application
    Filed: August 16, 2006
    Publication date: December 7, 2006
    Inventors: Masafumi Yamazaki, Toshiya Uchida
  • Patent number: 7113027
    Abstract: A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: September 26, 2006
    Assignee: Fujitsu Limited
    Inventors: Masafumi Yamazaki, Toshiya Uchida
  • Publication number: 20060181312
    Abstract: A semiconductor device includes a terminal configured to receive a first signal that is set from an exterior at a time of operation, a memory unit configured to retain a state of a setting fixedly regardless of whether at the time of operation or at a time of no operation and to produce at an output thereof a second signal responsive to the state of a setting, and an output driver unit coupled to the terminal and to the output of the memory unit to output an output signal by a drive power responsive to the first signal and the second signal.
    Type: Application
    Filed: June 14, 2005
    Publication date: August 17, 2006
    Inventors: Hiroyuki Kobayashi, Toshiya Uchida
  • Publication number: 20060092752
    Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.
    Type: Application
    Filed: January 28, 2005
    Publication date: May 4, 2006
    Inventors: Fusao Seki, Tatsushi Otsuka, Masanori Kurita, Shinnosuke Kamata, Toshiya Uchida, Hiroyoshi Tomita, Hiroyuki Kobayashi
  • Patent number: 6999358
    Abstract: A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: February 14, 2006
    Assignee: Fujitsu Limited
    Inventors: Yoshimasa Yagishita, Toshiya Uchida
  • Patent number: 6961830
    Abstract: A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: November 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Ikeda, Yasuharu Sato, Takaaki Suzuki, Toshiya Uchida, Kotoku Sato
  • Publication number: 20050201186
    Abstract: A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.
    Type: Application
    Filed: April 13, 2005
    Publication date: September 15, 2005
    Inventors: Masafumi Yamazaki, Toshiya Uchida
  • Publication number: 20050180242
    Abstract: A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.
    Type: Application
    Filed: April 12, 2005
    Publication date: August 18, 2005
    Inventors: Hiroyoshi Tomita, Toshiya Uchida
  • Publication number: 20050169071
    Abstract: A fuse circuit has an actual fuse circuit block and a fuse monitor circuit. The actual fuse circuit block stores fuse information; on the other hand, the fuse monitor circuit monitors whether a supply voltage has reached an information capturable voltage at which the fuse information from the actual fuse circuit block can be correctly captured.
    Type: Application
    Filed: March 29, 2005
    Publication date: August 4, 2005
    Inventors: Hiroyuki Kobayashi, Toshiya Uchida
  • Patent number: 6876225
    Abstract: The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: April 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshimasa Yagishita, Toshiya Uchida
  • Patent number: 6829195
    Abstract: A semiconductor memory device capable of shortening the command supply interval during random access and thus improving the transfer rate of input/output data. In response to a write command, identical data is written into multiple memory banks having identical addresses assigned thereto. At this time, a bank selection circuit sequentially selects the memory banks to initiate write operations in a staggered manner. Since the write operation can be started before all memory banks become idle, the interval between the supply of read command and the supply of write command can be shortened. Consequently, the number of commands supplied per given time can be increased, and since data signal can be input/output more frequently than in conventional devices, the data transfer rate (data bus occupancy) improves. As a result, the performance of a system to which the semiconductor memory device is mounted can be enhanced.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: December 7, 2004
    Assignee: Fujitsu Limited
    Inventors: Toshiya Uchida, Hiroyuki Kobayashi
  • Patent number: 6774655
    Abstract: A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: August 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasurou Matsuzaki, Masao Nakano, Toshiya Uchida, Atsushi Hatakeyama, Kenichi Kawasaki, Yasuhiro Fujii
  • Patent number: 6754126
    Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: June 22, 2004
    Assignee: Fujitsu Limited
    Inventors: Shusaku Yamaguchi, Toshiya Uchida, Yoshimasa Yagishita, Yoshihide Bando, Masahiro Yada, Masaki Okuda, Hiroyuki Kobayashi, Kota Hara, Shinya Fujioka, Waichiro Fujieda
  • Patent number: 6728157
    Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: April 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Yoshimasa Yagishita, Toshiya Uchida, Yoshihide Bando, Hiroyuki Kobayashi, Shusaku Yamaguchi, Masaki Okuda
  • Publication number: 20040062114
    Abstract: A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.
    Type: Application
    Filed: September 29, 2003
    Publication date: April 1, 2004
    Applicant: Fujitsu Limited
    Inventors: Yoshimasa Yagishita, Toshiya Uchida
  • Publication number: 20040051549
    Abstract: A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode.
    Type: Application
    Filed: July 21, 2003
    Publication date: March 18, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yasurou Matsuzaki, Masao Nakano, Toshiya Uchida, Atsushi Hatakeyama, Kenichi Kawasaki, Yasuhiro Fujii
  • Patent number: 6696859
    Abstract: The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: February 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Yoshimasa Yagishita, Toshiya Uchida
  • Publication number: 20040004883
    Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.
    Type: Application
    Filed: January 3, 2003
    Publication date: January 8, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yoshimasa Yagishita, Toshiya Uchida, Yoshihide Bando, Hiroyuki Kobayashi, Shusaku Yamaguchi, Masaki Okuda
  • Patent number: 6659167
    Abstract: A mix door (5) is arranged in air passages (10, 11) of an automotive air conditioning device. The mix door (5) is arranged to extend in a direction to shut an air flow blown from the upstream air passage (10) and swelled in a downstream direction with a predetermined radius of curvature. The door (5) is guided by arcuate cam grooves (19) and driven upward and downward to achieve open/close operation with the aid of a sliding mechanism (M). Compact construction, reduction in air flow resistance, smoothed handling, high sealing and high temperature controlling are achieved.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: December 9, 2003
    Assignee: Calsonic Kansei Corporation
    Inventors: Akihiro Tsurushima, Toshiyuki Yoshida, Masaharu Onda, Toshiya Uchida, Katsuaki Koshida, Katsuhiro Kurokawa