Patents by Inventor Toshiyuki Furusawa

Toshiyuki Furusawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240028529
    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Kenji SAKAUE, Toshiyuki FURUSAWA, Shinya TAKEDA
  • Patent number: 11853238
    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Kenji Sakaue, Toshiyuki Furusawa, Shinya Takeda
  • Publication number: 20230004506
    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Applicant: Kioxia Corporation
    Inventors: Kenji SAKAUE, Toshiyuki FURUSAWA, Shinya TAKEDA
  • Patent number: 11500793
    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: November 15, 2022
    Assignee: Kioxia Corporation
    Inventors: Kenji Sakaue, Toshiyuki Furusawa, Shinya Takeda
  • Publication number: 20210406204
    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.
    Type: Application
    Filed: January 26, 2021
    Publication date: December 30, 2021
    Applicant: Kioxia Corporation
    Inventors: Kenji SAKAUE, Toshiyuki FURUSAWA, Shinya TAKEDA
  • Patent number: 8598944
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nariyuki Fukuda, Noriyuki Moriyasu, Isao Ooigawa, Toshiyuki Furusawa, Satoko Kawakami, Hitoshi Nemoto, Hiroyuki Fujioka, Eiji Sawada, Tokio Tanaka
  • Publication number: 20130207692
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.
    Type: Application
    Filed: July 24, 2012
    Publication date: August 15, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nariyuki Fukuda, Noriyuki Moriyasu, Isao Ooigawa, Toshiyuki Furusawa, Satoko Kawakami, Hitoshi Nemoto, Hiroyuki Fujioka, Eiji Sawada, Tokio Tanaka
  • Patent number: 8067962
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: November 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
  • Publication number: 20110032262
    Abstract: A normal bus and an extension bus having the same bit width as the normal bus are provided. A line buffer has a plurality of line regions to store pixel data of input image data. A line buffer writing control portion controls a direction in which the pixel data is to be written to the line buffer. A line buffer reading control portion reads out the pixel data stored in the line buffer and to output the read out pixel data to the buses selectively. A frame memory writing control portion controls a destination in a frame memory to which the pixel data obtained from the buses is to be written. An address control portion controls a writing address in the frame memory. The line buffer writing control portion controls the writing direction in the line buffer in accordance with an image rotation command signal.
    Type: Application
    Filed: March 3, 2010
    Publication date: February 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki Furusawa, Hitoshi Nemoto, Isao Ooigawa, Nariyuki Fukuda, Hiroyuki Fujioka, Noriyuki Moriyasu
  • Publication number: 20100066419
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
    Type: Application
    Filed: September 4, 2009
    Publication date: March 18, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
  • Patent number: 7602211
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: October 13, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
  • Publication number: 20080238485
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
    Type: Application
    Filed: June 3, 2008
    Publication date: October 2, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mototsugu HAMADA, Tsuyoshi Nishikawa, Toshiyuki Furusawa
  • Patent number: 7397271
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: July 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
  • Patent number: 7216329
    Abstract: An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kitahara, Masaaki Yamada, Naoyuki Kawabe, Masahiro Kanazawa, Katsuhiro Seta, Toshiyuki Furusawa
  • Publication number: 20070075738
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series.
    Type: Application
    Filed: August 11, 2006
    Publication date: April 5, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
  • Patent number: 7109771
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 7088161
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050097494
    Abstract: An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.
    Type: Application
    Filed: April 2, 2004
    Publication date: May 5, 2005
    Inventors: Takeshi Kitahara, Masaaki Yamada, Naoyuki Kawabe, Masahiro Kanazawa, Katsuhiro Seta, Toshiyuki Furusawa
  • Patent number: 6861882
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050035803
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 23, 2004
    Publication date: February 17, 2005
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa