Patents by Inventor Toshiyuki Hiraki

Toshiyuki Hiraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11188488
    Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 30, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Nobuhiko Honda
  • Publication number: 20210365396
    Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Inventors: Sho YAMANAKA, Toshiyuki HIRAKI
  • Patent number: 11113218
    Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki
  • Patent number: 11100019
    Abstract: Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved. Each of a master A, a master B, and a master X issues an access request to a memory. A memory controller receives an access request through a bus. A central bus control unit controls output of an access request issued by a master to the memory controller through granting the master an access right to the memory. The central bus control unit manages the number of rights that can be granted, which indicates the number of the access rights that can be granted, based on an access size of an access request issued by the master to which the access right is granted, and performs grant of the access right within a range of the number of rights that can be granted.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Hayakawa, Toshiyuki Hiraki, Sho Yamanaka
  • Patent number: 11068425
    Abstract: A master issues an access request to the memory. The memory controller receives the access request via a bus. An access control unit controls an output of the access request issued by the master to the memory controller by the granting an access right. The access control unit manages a number of grantable rights indicating a number to which the access rights can be granted based on a weight of 0 or more and less than 1 according to a probability that the granted access right is used, and grants the access right within a range of the number of grantable rights.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Hayakawa, Toshiyuki Hiraki, Sho Yamanaka
  • Publication number: 20210141749
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 13, 2021
    Inventors: Katsuya MIZUMOTO, Toshiyuki HIRAKI, Nobuhiko HONDA, Sho YAMANAKA, Takahiro IRITA, Yoshihiko HOTTA
  • Patent number: 10929317
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: February 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuya Mizumoto, Toshiyuki Hiraki, Nobuhiko Honda, Sho Yamanaka, Takahiro Irita, Yoshihiko Hotta
  • Publication number: 20210026788
    Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Inventors: Sho YAMANAKA, Toshiyuki HIRAKI, Yoshihiko HOTTA, Takahiro IRITA
  • Patent number: 10831683
    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Publication number: 20190391943
    Abstract: A master issues an access request to the memory. The memory controller receives the access request via a bus. An access control unit controls an output of the access request issued by the master to the memory controller by the granting an access right. The access control unit manages a number of grantable rights indicating a number to which the access rights can be granted based on a weight of 0 or more and less than 1 according to a probability that the granted access right is used, and grants the access right within a range of the number of grantable rights.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 26, 2019
    Inventors: Yuki HAYAKAWA, Toshiyuki HIRAKI, Sho YAMANAKA
  • Publication number: 20190391942
    Abstract: Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved. Each of a master A, a master B, and a master X issues an access request to a memory. A memory controller receives an access request through a bus. A central bus control unit controls output of an access request issued by a master to the memory controller through granting the master an access right to the memory. The central bus control unit manages the number of rights that can be granted, which indicates the number of the access rights that can be granted, based on an access size of an access request issued by the master to which the access right is granted, and performs grant of the access right within a range of the number of rights that can be granted.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 26, 2019
    Inventors: Yuki HAYAKAWA, Toshiyuki HIRAKI, Sho YAMANAKA
  • Publication number: 20190196997
    Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 27, 2019
    Inventors: Sho YAMANAKA, Toshiyuki HIRAKI, Nobuhiko HONDA
  • Publication number: 20190057052
    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).
    Type: Application
    Filed: October 19, 2018
    Publication date: February 21, 2019
    Inventors: Sho YAMANAKA, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Publication number: 20190004983
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 3, 2019
    Inventors: Katsuya Mizumoto, Toshiyuki Hiraki, Nobuhiko Honda, Sho Yamanaka, Takahiro Irita, Yoshihiko Hotta
  • Patent number: 10108562
    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Publication number: 20170270063
    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).
    Type: Application
    Filed: October 1, 2015
    Publication date: September 21, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Sho YAMANAKA, Toshiyuki HIRAKI, Yoshihiko HOTTA, Takahiro IRITA
  • Publication number: 20080276021
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Application
    Filed: June 3, 2008
    Publication date: November 6, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Patent number: 7395364
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Publication number: 20070226391
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Application
    Filed: May 18, 2007
    Publication date: September 27, 2007
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki
  • Patent number: 7240138
    Abstract: A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: July 3, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Ryohei Higuchi, Toshiyuki Hiraki