Patents by Inventor Toshiyuki Honda

Toshiyuki Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11461253
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuya Mizumoto, Toshiyuki Hiraki, Nobuhiko Honda, Sho Yamanaka, Takahiro Irita, Yoshihiko Hotta
  • Publication number: 20190391762
    Abstract: A memory controller includes an address converter configured to convert an address designated by a host device for writing and reading into a physical address of a non-volatile memory, and an invalid-area manager configured to manage an invalid area of the non-volatile memory, the address converter making no reference to the invalid area, and, upon receipt of an invalid-data read command from the host device, data in the invalid area, managed by the invalid-area manager, of the non-volatile memory is output to the host device.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 26, 2019
    Inventors: Shigekazu KOGITA, Toshiyuki HONDA, Hirokazu SO, Masato SUTO
  • Publication number: 20190335062
    Abstract: A memory controller includes a data discard controller, calculates a physical address of discard object data designated by a logical address by a host device, and registers the calculated physical address as discard object data information. With respect to a predetermined command from the host device, the data discard controller outputs current discard object data information to the host device. When no command is received from the host device, the data discard controller physically erases the discard object data on the basis of the discard object data information.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 31, 2019
    Inventors: Hirokazu SOU, Toshiyuki HONDA, Shigekazu KOGITA, Masato SUTO
  • Patent number: 10324664
    Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 18, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hirokazu So, Toshiyuki Honda, Shigekazu Kogita
  • Patent number: 9965202
    Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 8, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigekazu Kogita, Hirokazu So, Toshiyuki Honda
  • Publication number: 20170269870
    Abstract: A memory controller controls a nonvolatile memory having physical blocks. The memory controller includes a control unit and a host interface unit. The control unit writes data into a physical block. The host interface unit receives and transmits data from and to the external device. The control unit manages first vacant blocks and second vacant blocks based on a physical-block management table for managing states of the physical blocks. The first vacant block can be used in garbage collection processing of arranging data stored in the nonvolatile memory. The second vacant block cannot be used in garbage collection processing. The control unit increases a quantity of the second vacant blocks when the control unit does not receive an instruction from the external device. The control unit writes data into the second vacant blocks when the control unit receives an instruction for writing data from the external device.
    Type: Application
    Filed: November 21, 2016
    Publication date: September 21, 2017
    Inventors: Hirokazu SO, Toshiyuki HONDA
  • Publication number: 20160283150
    Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Shigekazu KOGITA, Hirokazu SO, Toshiyuki HONDA
  • Publication number: 20160283163
    Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Hirokazu SO, Toshiyuki HONDA, Shigekazu KOGITA
  • Patent number: 9150396
    Abstract: The electric-vehicle control device is used in an electric vehicle which is provided with a vehicle body having a driving tire and an axle shaft and with a driving motor which imparts torque to the driving tire. The electric-vehicle control device issues a motor control command to the driving motor. The electric-vehicle control device is provided with a control unit, and the control unit gives feedback control to the driving motor by vibration parameters indicating vertical vibration of the electric vehicle at the center of the axle shaft.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: October 6, 2015
    Assignee: MITSUBISHI NICHIYU FORKLIFT CO., LTD.
    Inventors: Ryuichi Umehara, Osamu Nakakita, Masataka Kawaguchi, Toshiyuki Honda, Wataru Mizunuma
  • Patent number: 9092361
    Abstract: It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erasing in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data written by physical erasing after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: July 28, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshiyuki Honda, Kunihiro Maki, Shigekazu Kogita
  • Patent number: 9007864
    Abstract: A host device includes a voltage source which is connected to a voltage line via a host voltage switch and which supplies a first voltage to the voltage line, a host regulator which is connected to the voltage line and which outputs the first voltage or a second voltage that is lower than the first voltage, a host IO driver for driving a data line with the output of the host regulator as a power source, a host voltage detection circuit for detecting whether the voltage of the data line is the second voltage or a voltage that is higher than the second voltage, and a host control unit for detecting a mismatch of interface voltages between the host device and a memory card based on the output voltage of the host regulator and the detection result of the host voltage detection circuit.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Toshiyuki Honda
  • Patent number: 8898420
    Abstract: A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device comprises one or more non-volatile memories for storing data and a memory controller for carrying out control of the non-volatile memory. The memory controller writes data to the error correcting group and writes a provisional error correcting code with respect to the data to the parity table if a data size is smaller than the first size when writing the data.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Toshiyuki Honda
  • Patent number: 8856427
    Abstract: A non-volatile storage device comprises non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory. The memory controller stores second error correcting code as well as first error correcting code stored in the same page of the data. The memory controller, when writing data smaller than a predefined size, does not add the second error correcting code, and stores duplexed data of the data and the first correcting code in a different page. The memory controller, when reading, corrects data using the first and/or second correcting code. The valid data management table manages which logical block stores valid data with respect to an identical logical address.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 7, 2014
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Toshiyuki Honda
  • Patent number: 8819332
    Abstract: Upon copying data stored on a page in a copy source block of a nonvolatile memory to a page of a copy destination block, an access control unit of a memory controller copies data stored on a page associated with a first copy method to a page of the copy destination block after error correction by an error correction control unit copies data stored on a page associated with a second copy method to a page of the copy destination block without performing the error correction by the error correction control unit according to a copy mode stored in a copy mode storage area, and changes the copy mode associated with the copy destination block to a copy mode that is different from the copy mode of the copy source block.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Masato Suto, Toshiyuki Honda
  • Patent number: 8819329
    Abstract: A memory controller includes a reading/writing control unit for controlling writing and reading of data to and from a physical block of a nonvolatile memory, a writing mode table for storing one of a first writing mode of protecting data against a power shutdown during writing and a second writing mode of writing data at a higher speed than the first writing mode, and a setting unit for setting the writing mode received from an access device in a writing mode table. The reading/writing control unit performs data writing based on the writing mode that has been set in the writing mode table.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Masato Suto, Toshiyuki Honda, Keizo Miyata
  • Patent number: 8738974
    Abstract: The memory controller writes and reads data in and from a nonvolatile memory. The nonvolatile memory has a plurality of memory cell blocks, each memory cell block includes a plurality of multi-level cells each capable of storing m-bit data (m is a natural number of two or more), a first page to a m-th page are allocated to the respective m bits of the multi-level cell, the memory controller sequentially writes the data to the memory cells from the first page in ascending order, and comprises a backup unit, and when a write command is received from the outside of the memory controller, in a case where a data write destination of the data in the nonvolatile memory is a n-th (n is a natural number of two to m) page of the multi-level cell, and data is already written in the first to (n-1)th pages, the backup unit copies the already written data to a nonvolatile storable backup region.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: May 27, 2014
    Assignee: Panasonic Corporation
    Inventor: Toshiyuki Honda
  • Patent number: 8661186
    Abstract: An access device 100 includes an access speed information part 112 for informing an access speed required for data recording by the access device 100 to a nonvolatile memory device 200. The nonvolatile memory device includes an access condition determination part 212 for determining an access condition required for meeting the informed access speed and an access area determination unit 213 for determining an access area according to the determined access condition. The access device 100 informs the required access speed to the nonvolatile memory device 200 in advance so that the access condition determination part 212 and the access area determination part 213 in the nonvolatile memory device 200 realize data recording which meets the access speed informed in advance upon the data recording. Thus, it is possible to access all the nonvolatile memory devices at a desired speed regardless of difference in characteristics of the recording speed of each of the nonvolatile memory devices.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: February 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Toshiyuki Honda, Masahiro Nakanishi, Tadashi Ono, Tatsuya Adachi, Isao Kato
  • Patent number: 8656252
    Abstract: A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: February 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Toshiyuki Honda
  • Patent number: 8583858
    Abstract: A flash memory unit includes a plurality of physical blocks including a plurality of memory cells and serving as erase units of data, wherein each of the memory cells is capable of recording information of 1 bit or more and degradation in the characteristics of the memory cells differs according to the amount of information that is recorded. A controller includes a control unit for controlling the reading, writing and erasure of data to and from the flash memory unit, and a degradation level table for recording a degradation level of the memory cells in physical block units. The control unit stores, in the degradation level table, the degradation level of the memory cells according to the amount of information stored in the memory cells for each cycle of data erasure from the physical blocks.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventor: Toshiyuki Honda
  • Patent number: 8572307
    Abstract: A nonvolatile memory system includes a memory card (102) and host equipment (101). The memory card (102) includes a nonvolatile memory (106) including a plurality of physical blocks, and a memory controller (105) for writing data into the nonvolatile memory (106). The host equipment (101) provides to the memory card (102) an access instruction that designates a logical address and a channel number. The memory controller (105) has an address conversion function for converting the logical address into a physical address in the nonvolatile memory (106), a write destination determination function for determining in relation to the channel number a physical address in the nonvolatile memory (106) to which the data is to be written, and a channel management function for individually managing for each channel number a write state in which data of a smaller size than each physical block is written.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: October 29, 2013
    Assignee: Panasonic Corporation
    Inventor: Toshiyuki Honda