Patents by Inventor Toshiyuki Ishioka

Toshiyuki Ishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9077606
    Abstract: A data transmission system reduces the number of data transitions on signal lines in data transmission via parallel buses, and realizes a lower power consumption and lower EMI noise. A data transmission device transmits transmission data converted into encoded data, using n-bit signal lines. The data transmission device includes an arithmetic operation unit that generates difference data that represents the difference between first data for m bits of the transmission data and second data for m bits of the previous transmission data; and an encoding unit that encodes the difference data and generates m-bit encoded data. The encoding unit performs encoding to associate the encoded data with the difference data in such a manner that the number of bit inversions with respect to the encoded data associated with difference data “0” becomes smaller as the absolute value of the difference data becomes smaller.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: July 7, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Toshiyuki Ishioka
  • Patent number: 8978120
    Abstract: A communication control system pairs a first communication device with a second communication device, the first communication device includes a first image editing unit that edits an input image in accordance with a predetermined rule to generate a first authentication image, and a first transmission unit that transmits first authentication data representing the first authentication image and a first identifier for identifying the first communication device to a server device, the second communication device includes a second transmission unit that transmits second authentication data representing the second authentication image and a second identifier for identifying the second communication device to the server device, and the server device includes a pairing unit that pairs the first communication device with the second communication device in the case where it is determined that the first authentication data matches the second authentication data.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Toshiyuki Ishioka
  • Patent number: 8508394
    Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: August 13, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Ishioka, Takuji Aso
  • Patent number: 8451280
    Abstract: A display control device (1) comprises: a plurality of display devices (16a) and (16b); a display output section (18) which supplies image data to the display devices (16a) and (16b); a frame buffer (22) which temporarily stores the image data; and a buffer control section (24) which controls the frame buffer (22). The display output section (18) transmits the image data stored in the frame buffer (22) to the plurality of display devices (16a) and (16b), and reads, from an image data storage section (12), image data not stored in the frame buffer (22), so as to transmit the read image data to the display devices (16a) and (16b), and to write the read image data in the frame buffer (22). The buffer control section (24) is configured to prevent that image data, which are stored in the frame buffer (22) and which are not yet read, are overwritten by the image data read from the image data storage section (12). Thereby, it is possible to reduce the amount of memory access at low cost.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: May 28, 2013
    Assignee: Panasonic Corporation
    Inventor: Toshiyuki Ishioka
  • Publication number: 20130117834
    Abstract: A communication control system pairs a first communication device with a second communication device, the first communication device includes a first image editing unit that edits an input image in accordance with a predetermined rule to generate a first authentication image, and a first transmission unit that transmits first authentication data representing the first authentication image and a first identifier for identifying the first communication device to a server device, the second communication device includes a second transmission unit that transmits second authentication data representing the second authentication image and a second identifier for identifying the second communication device to the server device, and the server device includes a pairing unit that pairs the first communication device with the second communication device in the case where it is determined that the first authentication data matches the second authentication data.
    Type: Application
    Filed: April 27, 2012
    Publication date: May 9, 2013
    Inventor: Toshiyuki Ishioka
  • Patent number: 8433149
    Abstract: A system LSI serving as an image transmitter is a device for transmitting image data to a display device LCD connected by a data signal line. The system LSI comprises: an output image memory for storing the image data to be transmitted; a subtraction processing unit for reading the image data from the output image memory and obtaining the data of the difference between mutually adjacent pixels of the image data; and a data transmission unit for sequentially outputting a data signal, which expresses the difference data corresponding to the pixels as a binary number, to the data signal line in accordance with the arrangement of the pixels; wherein the data signal of the difference data in which the number of signal changes is reduced more than the case of outputting the pixel data to the data signal line is output.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: April 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshiteru Tanaka, Yasuo Kohashi, Toshiyuki Ishioka
  • Publication number: 20130093786
    Abstract: A video thumbnail display device includes a receiving unit which receives a selection of the first template included in the first thumbnail, a template determining unit which determines whether or not the second thumbnail including the second template which includes the same video data as that in the first template is displayed, an image obtaining unit which obtains the first display image in the first thumbnail and the second display image in the second thumbnail when the second thumbnail is determined to be displayed; a plural-video displaying unit which displays the first template in the first display region and the second template in the second display region, and an image displaying unit which displays the first display image in the region associated with the first display region and the second display image in the region associated with the second display region.
    Type: Application
    Filed: March 2, 2012
    Publication date: April 18, 2013
    Inventors: Naohisa Tanabe, Toshiyuki Ishioka
  • Publication number: 20120176261
    Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 12, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki ISHIOKA, Takuji ASO
  • Publication number: 20120179641
    Abstract: A content classification system provided with a content generating device for generating contents in sequence, the content classification system comprising: a detection unit operable to repeatedly detect a state of the content generating device, the state being a first state in which the content generating device is present at a predetermined position, or a second state in which the content generating device is not present at the predetermined position; and a classification unit operable to perform a classification process to classify two contents into different groups when there is a change in the state detected by the detection unit during a period between generations of the two contents by the content generating device, and classify the two contents into a same group when there is no change in the state detected by the detection unit during the period.
    Type: Application
    Filed: February 4, 2011
    Publication date: July 12, 2012
    Inventor: Toshiyuki Ishioka
  • Publication number: 20120072799
    Abstract: The present invention provides a data transmission system that reduces the number of data transitions on signal lines in data transmission via parallel buses between devices such as memory interfaces and liquid crystal interfaces, and can realize a lower power consumption and lower EMI noise. A data transmission device (100) transmits transmission data converted into encoded data, using n-bit (n being k×m, k and m being natural numbers each equal to or greater than 1) signal lines. The data transmission device (100) includes: an arithmetic operation unit (102) that generates difference data that represents the difference between first data for m bits of the transmission data and second data for m bits of the previous transmission data; and an encoding unit (103) that encodes the difference data and generates m-bit encoded data.
    Type: Application
    Filed: June 10, 2010
    Publication date: March 22, 2012
    Inventor: Toshiyuki Ishioka
  • Patent number: 8131968
    Abstract: An information processing device in which memory bands can be significantly cut. In the present device, an access determining/managing portion (105) determines whether or not write data meets access determination conditions when write-accessing a memory (104), and manages this determination result and access location data (an address in the memory (104)) during the write access as access determination results (107), and does not perform a write access if the write data does not meet the access determination conditions. On the other hand, the access determining/managing portion (105) references the access determination results (the access location data and determination result) when read-accessing the address, and if the access determination results meet the access determination conditions when read-accessing the address, the data determined by the access determining conditions is returned to the master, without read-accessing the memory (104).
    Type: Grant
    Filed: December 25, 2008
    Date of Patent: March 6, 2012
    Assignee: Panasonic Corporation
    Inventor: Toshiyuki Ishioka
  • Publication number: 20110216980
    Abstract: A system LSI serving as an image transmitter is a device for transmitting image data to a display device LCD connected by a data signal line. The system LSI comprises: an output image memory for storing the image data to be transmitted; a subtraction processing unit for reading the image data from the output image memory and obtaining the data of the difference between mutually adjacent pixels of the image data; and a data transmission unit for sequentially outputting a data signal, which expresses the difference data corresponding to the pixels as a binary number, to the data signal line in accordance with the arrangement of the pixels; wherein the data signal of the difference data in which the number of signal changes is reduced more than the case of outputting the pixel data to the data signal line is output.
    Type: Application
    Filed: November 13, 2009
    Publication date: September 8, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Yoshiteru Tanaka, Yasuo Kohashi, Toshiyuki Ishioka
  • Publication number: 20110037773
    Abstract: A display control device (1) comprises: a plurality of display devices (16a) and (16b); a display output section (18) which supplies image data to the display devices (16a) and (16b); a frame buffer (22) which temporarily stores the image data; and a buffer control section (24) which controls the frame buffer (22). The display output section (18) transmits the image data stored in the frame buffer (22) to the plurality of display devices (16a) and (16b), and reads, from an image data storage section (12), image data not stored in the frame buffer (22), so as to transmit the read image data to the display devices (16a) and (16b), and to write the read image data in the frame buffer (22). The buffer control section (24) is configured to prevent that image data, which are stored in the frame buffer (22) and which are not yet read, are overwritten by the image data read from the image data storage section (12). Thereby, it is possible to reduce the amount of memory access at low cost.
    Type: Application
    Filed: April 23, 2009
    Publication date: February 17, 2011
    Inventor: Toshiyuki Ishioka
  • Publication number: 20100262800
    Abstract: An information processing device in which memory bands can be significantly cut. In the present device, an access determining/managing portion (105) determines whether or not write data meets access determination conditions when write-accessing a memory (104), and manages this determination result and access location data (an address in the memory (104)) during the write access as access determination results (107), and does not perform a write access if the write data does not meet the access determination conditions. On the other hand, the access determining/managing portion (105) references the access determination results (the access location data and determination result) when read-accessing the address, and if the access determination results meet the access determination conditions when read-accessing the address, the data determined by the access determining conditions is returned to the master, without read-accessing the memory (104).
    Type: Application
    Filed: December 25, 2008
    Publication date: October 14, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Toshiyuki Ishioka
  • Patent number: 7343087
    Abstract: When advance prediction is conducted for overflows and underflows, which are both types of buffer errors, and the occurrence of a buffer error is predicted, frames that a viewer will be unlikely to notice even if playback is omitted or conducted for a different duration from a predetermined standard duration are omitted or played for a different playback duration.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: March 11, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Ishioka, Tsutomu Sekibe
  • Publication number: 20040141731
    Abstract: When advance prediction is conducted for overflows and underflows, which are both types of buffer errors, and the occurrence of a buffer error is predicted, frames that a viewer will be unlikely to notice even if playback is omitted or conducted for a different duration from a predetermined standard duration are omitted or played for a different playback duration.
    Type: Application
    Filed: November 6, 2003
    Publication date: July 22, 2004
    Inventors: Toshiyuki Ishioka, Tsutomu Sekibe
  • Publication number: 20040055013
    Abstract: To precisely adjust a playback reference time counter in a host device by transmitting a time adjustment signal included in a broadcast signal from a broadcast reception apparatus to the host device so that transmission delay inequalities do not occur in a broadcast receive/play system constituted by the host device, which is a portable information terminal or the like that functions to playback stream data based on the MPEG-2 system standard or the like, and the broadcast reception apparatus, which has a card configuration or the like, is mountable in a card slot or the like of the host device, and operates when mounted in and having power supplied from the host device, the broadcast reception apparatus conducts transmission/reception of reception control commands, response data and so forth with the host device via a connection terminal in a first group in sync with a clock signal from the host device, and also, in sync with a clock signal generated within the broadcast reception apparatus, extracts stream
    Type: Application
    Filed: June 30, 2003
    Publication date: March 18, 2004
    Inventors: Toshiyuki Ishioka, Tsutomu Sekibe
  • Publication number: 20030141994
    Abstract: Even when an address, which is output from a processor to a memory via an address bus, is scrambled, the address that the processor accesses immediately after reset can be obtained by monitoring the bus, and so there was a possibility that a scrambling key used for scrambling could be deciphered relatively easily. In this invention, a non-encoded area is set in which addresses are not encoded, in an address space. An encoding unit encodes the input address based on the input address and set non-encoded area. For example, addresses that can be obtained easily by monitoring the bus are placed in this non-encoded area. By doing this, security is improved.
    Type: Application
    Filed: January 27, 2003
    Publication date: July 31, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Ishioka, Tomohiko Kitamura, Hideyuki Kanzaki