Patents by Inventor Toshiyuki Kaya

Toshiyuki Kaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9832483
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20170337008
    Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 23, 2017
    Inventors: Seiji MOCHIZUKI, Katsushige Matsubara, Ren Imaoka, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 9800874
    Abstract: For a decoding apparatus based on H.265/HEVC with single-core or single-threaded hardware not parallelized, which executes decoding a plurality of tiles and filtering around a tile boundary, the disclosed invention is intended to reduce the frequency of access to decoded data around the boundaries between tiles stored in a frame memory for filtering such data or reduce the circuit size of a buffer that retains decoded data around the boundaries between tiles. The image decoding apparatus disclosed herein executes decoding and filtering in raster scan order across a screen independently of the sizes and positional relations of tiles. At a tile boundary, decoding proceeds to a right adjacent tile on the same row, rather than decoding coding blocks on one row down in the same tile, and filtering is also executed using decoded data of row-wise adjacent coding blocks.
    Type: Grant
    Filed: June 15, 2014
    Date of Patent: October 24, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 9786025
    Abstract: Signal processing including decoding and format conversion is executed on compressed image data at a high speed by simple control. A decoder decodes compressed image data in units of blocks and writes the decoded data in the blocks into a decoded data memory. A progress notification unit generates a progress signal indicating a state of progress that data is being decoded or written into the decoded data memory by the decoder and outputs the signal to a format conversion unit per picture. The format conversion unit reads out the decoded data from the decoded data memory and format-converts the data, and writes the format-converted data into a format-converted data memory. In reading out data from the decoded data memory, the format conversion unit acquires information indicating an address of decoded data readable from the decoded data memory from the progress signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki Kaya, Katsushige Matsubara
  • Publication number: 20170280155
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Kenichi IWATA, Seiji MOCHIZUKI, Toshiyuki KAYA, Ryoji HASHIMOTO
  • Publication number: 20170264820
    Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.
    Type: Application
    Filed: February 1, 2017
    Publication date: September 14, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Tetsuya SHIBAYAMA, Toshiyuki KAYA, Seiji MOCHIZUKI, Ryoji HASHIMOTO
  • Publication number: 20170257637
    Abstract: An in-vehicle system includes a camera having an encoder encoding video obtained by the camera, an image processing apparatus which receives the encoded video from the camera, and an image recognition processing circuit performing image recognition on decoded video data from the image processing apparatus. The image processing apparatus includes a codec processing circuit which decodes the encoded video, a plurality of image processing circuits which execute tasks in parallel, an estimating circuit which estimates estimation time in which a process of the task is completed in each of the image processing circuit on the basis of the number of access times to a bus which is obtained on the basis of a parameter of decoding used in the codec processing circuit, and a scheduling circuit which schedules tasks to be executed by the plurality of image processing circuit on the basis of the estimation time.
    Type: Application
    Filed: May 24, 2017
    Publication date: September 7, 2017
    Inventors: Katsushige MATSUBARA, Takayuki MATSUMI, Seiji MOCHIZUKI, Kenichi IWATA, Toshiyuki KAYA
  • Patent number: 9712842
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20170153838
    Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.
    Type: Application
    Filed: November 18, 2016
    Publication date: June 1, 2017
    Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI, Ryoji HASHIMOTO, Toshiyuki KAYA, Kimihiko NAKAZAWA, Takahiro IRITA, Tetsuji TSUDA
  • Patent number: 9667983
    Abstract: An image processing apparatus includes a request receiving unit that receives requests from a plurality of pieces of content, a variable-length code processing unit which decodes or encodes the content, a plurality of image signal processing units executing tasks according to the requests in parallel, an estimating unit that estimates estimate time by which a process of the task is completed in each of the image signal processing units on the basis of a parameter of decoding or encoding used in the variable-length code processing unit, and a scheduling unit that schedules tasks executed by the plurality of image signal processing units on the basis of estimation time estimated by the estimating unit.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 30, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Takayuki Matsumi, Seiji Mochizuki, Kenichi Iwata, Toshiyuki Kaya
  • Publication number: 20170094280
    Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 30, 2017
    Inventors: Ren IMAOKA, Seiji MOCHIZUKI, Toshiyuki KAYA, Kazushi AKIE, Ryoji HASHIMOTO
  • Publication number: 20170064312
    Abstract: Making effective use of an image encoder and an image decoder for processing a color image of a general-purpose standard bit depth, an image transmission device capable of transmitting/receiving a monochrome image of a higher bit depth is configured. An image transmission device includes an image encoder to encode a high bit-depth monochrome image and output encoded data and an image decoder to generate, by decoding the encoded data received via a transmission path, a high bit-depth monochrome image. The image encoder decomposes the input high bit-depth image data into plural bit planes corresponding to color image data of a standard bit depth and encodes the standard bit-depth color image data. The image decoder decodes the color image data of the standard bit depth and synthesizes, from the decoded standard bit-depth color image data, a high bit-depth monochrome image.
    Type: Application
    Filed: July 9, 2016
    Publication date: March 2, 2017
    Inventors: Tomohiro UNE, Takahiko SUGIMOTO, Kwangsoo PARK, Toshiyuki KAYA, Tetsuya SHIBAYAMA, Seiji MOCHIZUKI
  • Publication number: 20170039160
    Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.
    Type: Application
    Filed: March 12, 2015
    Publication date: February 9, 2017
    Inventors: Takahiko SUGIMOTO, Tomohiro UNE, Hiroshi UEDA, Ryoji HASHIMOTO, Toshiyuki KAYA
  • Publication number: 20170017591
    Abstract: A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.
    Type: Application
    Filed: May 2, 2016
    Publication date: January 19, 2017
    Inventors: Hiroshi UEDA, Ren IMAOKA, Seiji MOCHIZUKI, Toshiyuki KAYA
  • Publication number: 20160283430
    Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).
    Type: Application
    Filed: December 10, 2015
    Publication date: September 29, 2016
    Inventors: Hiroshi UEDA, Seiji MOCHIZUKI, Toshiyuki KAYA, Kenichi IWATA, Katsushige MATSUBARA
  • Publication number: 20160255365
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20160227236
    Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.
    Type: Application
    Filed: December 16, 2015
    Publication date: August 4, 2016
    Inventors: Keisuke MATSUMOTO, Katsushige MATSUBARA, Seiji MOCHIZUKI, Toshiyuki KAYA, Hiroshi UEDA
  • Publication number: 20160198174
    Abstract: A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.
    Type: Application
    Filed: October 30, 2015
    Publication date: July 7, 2016
    Inventors: Seiji MOCHIZUKI, Toshiyuki KAYA, Hiroshi UEDA, Tetsuya SHIBAYAMA
  • Patent number: 9363527
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: June 7, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20160007025
    Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.
    Type: Application
    Filed: June 24, 2015
    Publication date: January 7, 2016
    Inventors: Toshiyuki KAYA, Seiji MOCHIZUKI, Tetsuya SHIBAYAMA, Kenichi IWATA, Hiroshi UEDA, Ren IMAOKA