Patents by Inventor Toshiyuki Kouchi

Toshiyuki Kouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352093
    Abstract: According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.
    Type: Application
    Filed: March 3, 2023
    Publication date: November 2, 2023
    Applicant: Kioxia Corporation
    Inventors: Junya MATSUNO, Yasuhiro HIRASHIMA, Toshiyuki KOUCHI
  • Publication number: 20230326535
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 12, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
  • Patent number: 11715529
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 1, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Publication number: 20230204614
    Abstract: In a dispensing system, a body is arranged outside a specimen processing cabinet, and in a state where a hand and a dispenser are inserted into the specimen processing cabinets, a specimen accommodated in a specimen container held by the hand is dispensed into a dispensing container by the dispenser.
    Type: Application
    Filed: May 27, 2021
    Publication date: June 29, 2023
    Applicants: KAWASAKI JUKOGYO KABUSHIKI KAISHA, SYSMEX CORPORATION
    Inventors: Noboru TAKAGI, Atsushi KAMEYAMA, Eiji YOSHIKUWA, Toshiyuki TSUJIMORI, Shogo KUBOTA, Satoshi OUCHI, Yukio IWASAKI, Yasuhiro KOUCHI, Soichi OUE, Hironori KOBAYASHI, Yutaka MAEDA, Takayuki KOSHIHARA
  • Publication number: 20220189563
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 16, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
  • Patent number: 11295821
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: April 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Publication number: 20210151114
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
  • Patent number: 10950314
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Publication number: 20200211659
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
  • Patent number: 10636499
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Patent number: 10438670
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Patent number: 10438929
    Abstract: According to one embodiment, M (M represents an integer of 2 or larger) semiconductor chips and through electrodes for N (N represents an integer of 2 or larger) channels are provided. The M semiconductor chips are stacked in sequence. The through electrodes are embedded in the semiconductor chips to connect electrically the semiconductor chips in the direction of stacking. The connection destination of the through electrodes are exchanged between one or more upper and lower layers of the semiconductor chips.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshiyuki Kouchi, Masaru Koyanagi
  • Patent number: 10423666
    Abstract: A semiconductor device that writes, into respective memory spaces of a plurality of separate memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divided data are assigned respectively to the separate memories, and, by employing each divided data as an address, entry addresses corresponding to the divided data are written sequentially into memory spaces specified by memory addresses of the separate memories (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to a single one of the plurality of pieces of divided data is successfully written into a memory space, the first writing process is ended. Second write processing to a verification memory may also be performed. Key data may be written to a backup memory when a whole collision occurs.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 24, 2019
    Assignee: NAGASE & CO., LTD.
    Inventors: Masato Nishizawa, Kaoru Kobayashi, Kanji Otsuka, Yoichi Sato, Toshiyuki Kouchi, Minoru Uwai
  • Publication number: 20190279727
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
  • Patent number: 10381092
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Patent number: 10204900
    Abstract: A semiconductor device includes a first circuit configured to generate a current corresponding to the input signal, a second circuit configured to generate a voltage corresponding to the current generated by the first circuit, a constant current source, a transistor that includes a drain terminal receiving a current from the constant current source and a gate terminal to which the voltage corresponding to the current generated by the first circuit is applied, and an amplification circuit configured to amplify a difference voltage between a drain voltage of the transistor and a reference voltage and output the amplified difference voltage as an output signal corresponding to the input signal.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Toshiyuki Kouchi, Shinya Okuno
  • Patent number: 10180692
    Abstract: A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Kouchi
  • Publication number: 20180294038
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
  • Patent number: 10026485
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Publication number: 20180129756
    Abstract: Disclosed is a semiconductor device that writes, into respective memory spaces of a plurality of divisional memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divisional data are assigned respectively to the divisional memories, and, by employing each divisional data as an address, an entry address corresponding to said divisional data is written sequentially into a memory space specified by a memory address of each said divisional memory (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to one of the plurality of pieces of divisional data is successfully written into a memory space, the first writing process is ended.
    Type: Application
    Filed: April 18, 2016
    Publication date: May 10, 2018
    Applicant: NAGASE & CO., LTD.
    Inventors: Masato NISHIZAWA, Kaoru KOBAYASHI, Kanji OTSUKA, Yoichi SATO, Toshiyuki KOUCHI, Minoru UWAI