Patents by Inventor Toshiyuki Miyanagi
Toshiyuki Miyanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9601404Abstract: A temperature of a semiconductor element is measured based on a temperature coefficient of a voltage between the first electrode and the second electrode when no heat is generated when causing a constant current of an extent such that the semiconductor element does not generate heat to be input wherein current is caused to flow from a third electrode to a second electrode in accordance with voltage applied between a first electrode and the second electrode. Also, a constant current such that the semiconductor element generates heat is input into the third electrode, with voltage applied between the first electrode and second electrode of the semiconductor element kept constant, and power is measured based on the current such that the semiconductor element generates heat and on voltage when heat is generated between the third electrode and second electrode when the semiconductor element generates heat.Type: GrantFiled: June 11, 2014Date of Patent: March 21, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshiyuki Miyanagi, Yuichiro Hinata
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Patent number: 9355930Abstract: A surface of a power semiconductor chip, mounted within a power semiconductor module and not being opposed to a wiring thin film, and a surface of a bonding wire are sealed with a resin that does not contain a thermally-conductive filler, and the resin that does not contain a thermally-conductive filler is sealed with a resin that contains a thermally-conductive filler.Type: GrantFiled: March 12, 2015Date of Patent: May 31, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventor: Toshiyuki Miyanagi
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Patent number: 9165871Abstract: In some aspects of the invention, semiconductor unit can produce chips performing uniform parallel operation and a low-thermal-resistance. Aspects of the invention can include a plurality of small semiconductor chips of one and the same kind formed by use of an SiC substrate, which is a wide gap substrate are sandwiched between two conductive plates. In this manner, there can be provided a high-reliability semiconductor unit in which parallel operation of the semiconductor chips is uniformized so that breakdown caused by current concentration can be prevented.Type: GrantFiled: November 13, 2013Date of Patent: October 20, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventor: Toshiyuki Miyanagi
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Publication number: 20150187674Abstract: A surface of a power semiconductor chip, mounted within a power semiconductor module and not being opposed to a wiring thin film, and a surface of a bonding wire are sealed with a resin that does not contain a thermally-conductive filler, and the resin that does not contain a thermally-conductive filler is sealed with a resin that contains a thermally-conductive filler.Type: ApplicationFiled: March 12, 2015Publication date: July 2, 2015Inventor: Toshiyuki MIYANAGI
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Publication number: 20150003492Abstract: A temperature of a semiconductor element is measured based on a temperature coefficient of a voltage between the first electrode and the second electrode when no heat is generated when causing a constant current of an extent such that the semiconductor element does not generate heat to be input wherein current is caused to flow from a third electrode to a second electrode in accordance with voltage applied between a first electrode and the second electrode. Also, a constant current such that the semiconductor element generates heat is input into the third electrode, with voltage applied between the first electrode and second electrode of the semiconductor element kept constant, and power is measured based on the current such that the semiconductor element generates heat and on voltage when heat is generated between the third electrode and second electrode when the semiconductor element generates heat.Type: ApplicationFiled: June 11, 2014Publication date: January 1, 2015Inventors: Toshiyuki MIYANAGI, Yuichiro HINATA
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Publication number: 20140061673Abstract: In some aspects of the invention, semiconductor unit can produce chips performing uniform parallel operation and a low-thermal-resistance. Aspects of the invention can include a plurality of small semiconductor chips of one and the same kind formed by use of an SiC substrate, which is a wide gap substrate are sandwiched between two conductive plates. In this manner, there can be provided a high-reliability semiconductor unit in which parallel operation of the semiconductor chips is uniformized so that breakdown caused by current concentration can be prevented.Type: ApplicationFiled: November 13, 2013Publication date: March 6, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventor: Toshiyuki MIYANAGI
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Patent number: 8455269Abstract: In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C.Type: GrantFiled: August 4, 2006Date of Patent: June 4, 2013Assignee: Central Research Institute of Electric Power IndustryInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Patent number: 8367510Abstract: In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.Type: GrantFiled: September 1, 2006Date of Patent: February 5, 2013Assignee: Central Research Institute of Electric Power IndustryInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Masahiro Nagano, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Patent number: 8178940Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.Type: GrantFiled: November 22, 2006Date of Patent: May 15, 2012Assignee: Central Research Institute of Electric Power IndustryInventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
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Patent number: 8154026Abstract: In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage.Type: GrantFiled: December 13, 2006Date of Patent: April 10, 2012Assignee: Central Research Institute of Electric Power IndustryInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Tomonori Nakamura
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Patent number: 7960257Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7960738Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7960737Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7902054Abstract: A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode.Type: GrantFiled: February 15, 2007Date of Patent: March 8, 2011Assignee: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Tomonori Nakamura, Toshiyuki Miyanagi
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Publication number: 20100258817Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20100261333Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20100258816Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Joji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7768017Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: December 1, 2004Date of Patent: August 3, 2010Assignees: The Kansai Electric Co., Inc., Central Research Institution of Electrical Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20090317983Abstract: In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.Type: ApplicationFiled: September 1, 2006Publication date: December 24, 2009Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Masahiro Nagano, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Publication number: 20090243026Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.Type: ApplicationFiled: November 22, 2006Publication date: October 1, 2009Applicant: Central Research Institute of Electric Power IndustryInventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi