Patents by Inventor Travis J. Anderson
Travis J. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170358670Abstract: Systems and method are provided for depositing metal on GaN transistors after gate formation using a metal nitride Schottky gate. Embodiments of the present disclosure use a “diamond last” process using thermally stable metal nitride gate electrodes to enable thicker heat spreading films and facilitate process integration. In an embodiment, the “diamond last” process with high thermal conductivity diamond is enabled by the integration of thermally stable metal-nitride gate electrodes.Type: ApplicationFiled: June 8, 2017Publication date: December 14, 2017Inventors: Francis J. Kub, Travis J. Anderson, Virginia D. Wheeler, Andrew D. Koehler, Karl D. Hobart
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Publication number: 20170338332Abstract: Passivated AlGaN/GaN HEMTs having no plasma damage to the AlGaN surface and methods for making the same. In a first embodiment, a thin HF SiN barrier layer is deposited on the AlGaN surface after formation of the gate. A thick HF/LF SiN layer is then deposited, the thin HF SiN layer and the thick HF/LF Sin layer comprising bi-layer SiN passivation on the HEMT. In a second embodiment, a first thin HF SiN barrier layer is deposited on the AlGaN surface before formation of the gate and is annealed. Following annealing of the first SiN layer, the gate is formed, and a second HF SiN barrier layer is deposited, followed by a thick HF/LF SiN layer, the three SiN layers comprising tri-layer SiN passivation on the HEMT.Type: ApplicationFiled: May 11, 2017Publication date: November 23, 2017Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Marko J. Tadjer, Andrew D. Koehler, Travis J. Anderson, Karl D. Hobart
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Publication number: 20170330950Abstract: Systems and methods are provided that enable the production of semiconductor devices having a metal nitride layer in direct contact with a semiconductor layer to form a Schottky diode, such as a TiN gate on an AlGaN/GaN high electron mobility transistor (HEMT). Metal nitrides offer exceptional thermal stability and a lower diffusion coefficient. Technology enabled by embodiments of the present disclosure improves the reliability of GaN-based microwave power transistors.Type: ApplicationFiled: May 16, 2017Publication date: November 16, 2017Inventors: Travis J. Anderson, Virginia D. Wheeler, David Shahin, Andrew D. Koehler, Karl D. Hobart, Francis J. Kub, Marko J. Tadjer
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Publication number: 20170316952Abstract: An method of annealing by: providing a substrate having a III-nitride, sapphire, silicon, diamond, gallium arsenide, or silicon carbide surface; depositing a layer of a transition metal nitride directly on the surface; and annealing the substrate at at least 900° C. in an oxygen-free environment. An article having: a substrate having a III-nitride, sapphire, silicon, diamond, gallium arsenide, or silicon carbide surface; and a layer of a transition metal nitride directly on the surface.Type: ApplicationFiled: May 1, 2017Publication date: November 2, 2017Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Travis J. Anderson, Boris N. Feygelson, Andrew D. Koehler, Karl D. Hobart, Francis J. Kub, Jordan Greenlee
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Patent number: 9685513Abstract: Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer.Type: GrantFiled: October 23, 2013Date of Patent: June 20, 2017Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Karl D. Hobart
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Publication number: 20170125557Abstract: A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler
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Patent number: 9590081Abstract: A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.Type: GrantFiled: November 25, 2015Date of Patent: March 7, 2017Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler
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Patent number: 9543168Abstract: A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (MRTA) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable. The SMRTA method can be used to form p-type and n-type semiconductor regions in doped III-nitride semiconductors, SiC, and diamond.Type: GrantFiled: February 4, 2016Date of Patent: January 10, 2017Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Boris N. Feigelson, Jordan Greenlee, Travis J. Anderson, Francis J. Kub
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Patent number: 9490356Abstract: Methods for forming a high-quality III-nitride passivation layer on an AlGaN/GaN HEMT. A III-nitride passivation layer is formed on the surface of an AlGaN/GaN HEMT by means of atomic layer epitaxy (ALE), either before or after deposition of a gate metal electrode on the AlGaN barrier layer. Depending on the gate metal and/or the passivation material used, the III-nitride passivation layer can be formed by ALE at temperatures between about 300° C. and about 85020 C. In a specific embodiment, the III-nitride passivation layer can be an AlN layer formed by ALE at about 550° C. after deposition of a Schottky metal gate electrode. The III-nitride passivation layer can be grown so as to conformally cover the entire device, providing a hermetic seal that protects the against environmental conditions.Type: GrantFiled: March 25, 2016Date of Patent: November 8, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Andrew D. Koehler, Travis J. Anderson, Karl D. Hobart, Francis J. Kub
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Patent number: 9466684Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.Type: GrantFiled: March 25, 2016Date of Patent: October 11, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Andrew D. Koehler, Travis J. Anderson, Marko J. Tadjer, Karl D. Hobart, Tatyana I. Feygelson
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Publication number: 20160233108Abstract: A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (MRTA) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable. The SMRTA method can be used to form p-type and n-type semiconductor regions in doped III-nitride semiconductors, SiC, and diamond.Type: ApplicationFiled: February 4, 2016Publication date: August 11, 2016Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Boris N. Feigelson, Jordan Greenlee, Travis J. Anderson, Francis J. Kub
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Publication number: 20160211341Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.Type: ApplicationFiled: March 25, 2016Publication date: July 21, 2016Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Andrew D. Koehler, Travis J. Anderson, Marko J. Tadjer, Karl D. Hobart, Tatyana I. Feygelson
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Publication number: 20160204222Abstract: Methods for forming a high-quality III-nitride passivation layer on an AlGaN/GaN HEMT. A III-nitride passivation layer is formed on the surface of an AlGaN/GaN HEMT by means of atomic layer epitaxy (ALE), either before or after deposition of a gate metal electrode on the AlGaN barrier layer. Depending on the gate metal and/or the passivation material used, the III-nitride passivation layer can be formed by ALE at temperatures between about 300° C. and about 85020 C. In a specific embodiment, the III-nitride passivation layer can be an AlN layer formed by ALE at about 550° C. after deposition of a Schottky metal gate electrode. The III-nitride passivation layer can be grown so as to conformally cover the entire device, providing a hermetic seal that protects the against environmental conditions.Type: ApplicationFiled: March 25, 2016Publication date: July 14, 2016Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Andrew D. Koehler, Travis J. Anderson, Karl D. Hobart, Francis J. Kub
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Patent number: 9331163Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.Type: GrantFiled: August 28, 2014Date of Patent: May 3, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Andrew D. Koehler, Travis J. Anderson, Marko J. Tadjer, Tatyana I. Feygelson, Karl D. Hobart
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Patent number: 9305858Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.Type: GrantFiled: August 7, 2015Date of Patent: April 5, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
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Publication number: 20160087087Abstract: A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.Type: ApplicationFiled: November 25, 2015Publication date: March 24, 2016Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler
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Patent number: 9275998Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride grown epitaxially on a substrate, a barrier, a two-dimensional hole gas in the barrier layer material at the heterointerface of the first material, and wherein the gallium-polar III-Nitride material comprises III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face of a substrate so that the gallium-polar (0001) face is the dominant face for growth of III-Nitride epitaxial layer growth material, growing a GaN epitaxial layer, doping, growing a barrier, etching, forming a contact, performing device isolation, defining a gate opening, defining gate metal, making a contact window, and depositing and defining a thick metal.Type: GrantFiled: April 29, 2014Date of Patent: March 1, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
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Patent number: 9246305Abstract: A light-emitting device having one or more diamond layers integrated therein and methods for forming a light-emitting device with integrated diamond layers. The diamond is grown either directly on the semiconductor material comprising the light-emitting structure, on a nucleation layer deposited on the semiconductor material, or on a dielectric layer deposited on the semiconductor material before growth of the diamond layer. The device can include a trench or thermal shunt formed in the substrate on the backside of the device, or can include a heat sink to provide additional thermal management.Type: GrantFiled: March 20, 2015Date of Patent: January 26, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Karl D. Hobart
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Patent number: 9236432Abstract: A graphene base transistor with reduced collector area comprising an electron injection region, an electron collection region, and a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.Type: GrantFiled: February 12, 2014Date of Patent: January 12, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler
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Publication number: 20150348866Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.Type: ApplicationFiled: August 7, 2015Publication date: December 3, 2015Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson