Abstract: A debug system for debugging a logic design includes an adaptor and a debug station connected to the adaptor. The logic design includes a plurality of design modules. The adaptor is configured to receive an emulation output of the logic design. The emulation output includes a design snapshot of the logic design and input signals to the logic design that both are recorded during an emulation process of the logic design. The debug station is configured to generate, based on the emulation output and a netlist of a design module of the logic design, an emulation history of the design module.

Abstract: An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a ‘platform neutral debug station.’ The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.

Abstract: A method for receiving a circuit layout including modules in a hierarchical structure. The method includes selecting a module in the hierarchical structure, identifying multiple toggling netlists in the module during multiple clock cycles, grouping the toggling netlists into clusters based on a toggle weight factor, and finding an average toggle weight factor for each cluster. The method includes generating instrument logic to determine a power consumption of the circuit layout based on a number of toggling netlists in each cluster for each clock cycle, and on the average toggle weight factor for each cluster, merging, with a compiler tool, the instrument logic with the circuit layout into an executable file for an emulator tool. The method includes evaluating the power consumption of the circuit layout with the emulator tool; and modifying the circuit layout when the power consumption of the circuit layout exceeds a pre-selected threshold.

Abstract: An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a ‘platform neutral debug station.’ The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.

Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.

Abstract: Essential information for system operations, memory analysis, and design signal analysis is captured while a hardware based verification platform is performing emulation and testing. This recorded information is then accessible via a memory device and can be used to perform offline debugging with a virtual verification machine (VVM). Users can then release the shared resources and run operation commands to control replay of the design test or emulation in offline mode. Users can access any point in time of the recorded emulation in order to perform detailed design analysis and debugging operations. Offline analysis and debugging may include running certain design cycles, rerunning the emulation until the design reaches a certain state, evaluating memory contents in the design, evaluating design signals for any node in the design, etc.

Abstract: A system and method for selectively capturing and storing emulation data results from a hardware emulation system, which reduces the data bandwidth requirement and the unnecessary consumption of the DRAM memory capacity by uninteresting data. According to one embodiment, a system comprises a trace array for storing one or more frames of data; a first set of hardware control bits that enables the trace array to selectively capture non-continuous windows of data within a frame of data; a data capture card; and a second set of hardware control bits that enables the data capture card to capture a select frame of data from the one or more frames of data stored on the trace array.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract: Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s). The IP provider then can debug the IP. In one aspect, the techniques give the IP provider(s) specific information about the nature of the defect, facilitating the provider's efforts to debug the IP.

Abstract: The present patent document relates a method and apparatus for compressing probe system data in hardware functional verification systems used to verify user logic designs. Such systems can create large amounts of data every data cycle, which can include many bits that do not toggle from one cycle to the next. Compressing such data is possible by arranging the data in bytes and determining which bytes contain bits that have changed. A status byte may be generated that conveys which bytes contain changed bits. Together the status byte and only the bytes that contain changed bits are transmitted to a host workstation, saving bandwidth on the communication interface.

Abstract: The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract: A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.

Abstract: A system and method for selectively capturing and storing emulation data results from a hardware emulation system, which reduces the data bandwidth requirement and the unnecessary consumption of the DRAM memory capacity by uninteresting data. According to one embodiment, a system comprises a trace array for storing one or more frames of data; a first set of hardware control bits that enables the trace array to selectively capture non-continuous windows of data within a frame of data; a data capture card; and a second set of hardware control bits that enables the data capture card to capture a select frame of data from the one or more frames of data stored on the trace array.

Abstract: A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract: The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.