Patents by Inventor Tse-Mian KUO

Tse-Mian KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395635
    Abstract: A standby current detection circuit includes multiple first transistors. The first transistors are coupled in series to form a first detection circuit string, where N is a positive integer. The first detection circuit string is disposed on a scribe lane of a wafer, and the first detection circuit string is operated in a standby state and serves as a test medium for a standby current.
    Type: Application
    Filed: June 13, 2023
    Publication date: November 28, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Bo-Lun Wu, Tse-Mian Kuo, Po-Yen Hsu
  • Publication number: 20240387666
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a floating gate, a dielectric stack, a control gate, and a protective layer. The substrate includes an active region and a peripheral region. The floating gate is disposed on the substrate. The dielectric stack is disposed on the floating gate. The control gate is disposed on the dielectric stack. The protective layer is disposed on the control gate. The protective layer located in the active region has a stepped portion.
    Type: Application
    Filed: September 22, 2023
    Publication date: November 21, 2024
    Inventors: Po-Yen HSU, Bo-Lun WU, Tse-Mian KUO
  • Patent number: 12114579
    Abstract: A method of fabricating a resistive random access memory cell includes the following steps. A second sacrificial layer is formed around a patterned stacked layer. An opening passing through first conductive layers and first sacrificial layers of the patterned stacked layer is formed. A second conductive layer is formed in the opening, and the second conductive layer and the first conductive layers form a first electrode layer. The first sacrificial layers and the second sacrificial layer are removed. A variable resistance layer and an oxygen reservoir layer are formed. The oxygen reservoir layer is patterned to form a patterned oxygen reservoir layer and expose the variable resistance layer. A second dielectric layer is formed on the variable resistance layer and the patterned oxygen reservoir layer. A second electrode is formed in the second dielectric layer.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: October 8, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Patent number: 12029049
    Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 2, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo, Wei-Che Chang, Shuo-Che Chang
  • Publication number: 20240147726
    Abstract: A method of forming a memory structure is provided. The method includes providing a substrate, wherein the substrate has a plurality of isolation structures, and the isolation structures include a plurality of first protrusions protruding above the substrate; replacing the first protrusions with a plurality of second protrusions to define a plurality of predetermined regions of floating gates between the second protrusions. The replacing step includes forming an insulation filling material between the first protrusions and on the substrate, and performing a patterning process to the insulation filling and the first protrusions to form second protrusions to define the predetermined regions of the floating gates, and forming a plurality of floating gates in the predetermined regions of the floating gates.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Inventors: Bo-Lun WU, Po-Yen HSU, Tse-Mian KUO
  • Publication number: 20230422638
    Abstract: A method of fabricating a resistive random access memory cell includes the following steps. A second sacrificial layer is formed around a patterned stacked layer. An opening passing through first conductive layers and first sacrificial layers of the patterned stacked layer is formed. A second conductive layer is formed in the opening, and the second conductive layer and the first conductive layers form a first electrode layer. The first sacrificial layers and the second sacrificial layer are removed. A variable resistance layer and an oxygen reservoir layer are formed. The oxygen reservoir layer is patterned to form a patterned oxygen reservoir layer and expose the variable resistance layer. A second dielectric layer is formed on the variable resistance layer and the patterned oxygen reservoir layer. A second electrode is formed in the second dielectric layer.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Patent number: 11800815
    Abstract: A resistive random access memory cell includes a first electrode layer, an oxygen reservoir layer, a variable resistance layer, and a second electrode. The first electrode layer is located on a dielectric layer, and includes a body part extending in a first direction and multiple extension parts connected to a sidewall of the body part and extending in a second direction. The second direction is perpendicular to the first direction. The oxygen reservoir layer covers the first electrode layer. The variable resistance layer is located between the first electrode layer and the oxygen reservoir layer. The second electrode is located above a top surface of the oxygen reservoir layer and around an upper sidewall of the oxygen reservoir layer.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 24, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Patent number: 11793094
    Abstract: A resistive memory including a substrate, a first electrode, a second electrode, a resistance changeable layer and an oxygen reservoir layer is provided. The first electrode is located on the substrate. The second electrode is located between the first electrode and the substrate. The resistance changeable layer is located between the first electrode and the second electrode. The oxygen reservoir layer is located between the first electrode and the resistance changeable layer. The oxygen reservoir layer includes a first portion, a second portion and a third portion. The second portion is connected to one side of the first portion. The third portion is connected to the other side of the first portion. A thickness of the first portion is greater than a thickness of the second portion and a thickness of the third portion. The first portion of the oxygen reservoir layer protrudes toward the first electrode.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: October 17, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Patent number: 11793095
    Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Shih-Ning Tsai, Tse-Mian Kuo
  • Patent number: 11785868
    Abstract: A semiconductor structure includes a substrate, a first electrode, a vacancy supply layer, a sidewall barrier layer, an oxygen reservoir layer, a resistive switching layer, and a second electrode. The first electrode is disposed on the substrate. The vacancy supply layer is disposed on the first electrode. The sidewall barrier layer is disposed on the first electrode. The oxygen reservoir layer is disposed on the first electrode. The sidewall barrier layer is disposed between the oxygen reservoir layer and the vacancy supply layer. The resistive switching layer is disposed on the vacancy supply layer. The second electrode is disposed on the resistive switching layer.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: October 10, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Patent number: 11495637
    Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 8, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Shih-Ning Tsai, Bo-Lun Wu, Tse-Mian Kuo
  • Publication number: 20220352463
    Abstract: A resistive random access memory cell includes a first electrode layer, an oxygen reservoir layer, a variable resistance layer, and a second electrode. The first electrode layer is located on a dielectric layer, and includes a body part extending in a first direction and multiple extension parts connected to a sidewall of the body part and extending in a second direction. The second direction is perpendicular to the first direction. The oxygen reservoir layer covers the first electrode layer. The variable resistance layer is located between the first electrode layer and the oxygen reservoir layer. The second electrode is located above a top surface of the oxygen reservoir layer and around an upper sidewall of the oxygen reservoir layer.
    Type: Application
    Filed: September 2, 2021
    Publication date: November 3, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Publication number: 20220293851
    Abstract: A semiconductor structure includes a substrate, a first electrode, a vacancy supply layer, a sidewall barrier layer, an oxygen reservoir layer, a resistive switching layer, and a second electrode. The first electrode is disposed on the substrate. The vacancy supply layer is disposed on the first electrode. The sidewall barrier layer is disposed on the first electrode. The oxygen reservoir layer is disposed on the first electrode. The sidewall barrier layer is disposed between the oxygen reservoir layer and the vacancy supply layer. The resistive switching layer is disposed on the vacancy supply layer. The second electrode is disposed on the resistive switching layer.
    Type: Application
    Filed: November 12, 2021
    Publication date: September 15, 2022
    Inventors: Po-Yen HSU, Bo-Lun WU, Tse-Mian KUO
  • Patent number: 11424407
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first dielectric layer, a bottom electrode, a resistance switching layer, an oxygen exchange layer, a barrier layer and a top electrode. The first dielectric layer is disposed on the substrate. The bottom electrode is disposed on the first dielectric layer. The resistance switching layer is disposed on the bottom electrode. The oxygen exchange layer is disposed on the resistance switching layer. A contact area between the oxygen exchange layer and the resistance switching layer is smaller than a top surface area of the resistance switching layer. The barrier layer is disposed on the oxygen exchange layer. The top electrode is disposed on the barrier layer.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 23, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Publication number: 20220216401
    Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.
    Type: Application
    Filed: August 3, 2021
    Publication date: July 7, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Shih-Ning Tsai, Tse-Mian Kuo
  • Publication number: 20220190033
    Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Po-Yen HSU, Bo-Lun WU, Tse-Mian KUO, Wei-Che CHANG, Shuo-Che CHANG
  • Publication number: 20220173314
    Abstract: A resistive memory including a substrate, a first electrode, a second electrode, a resistance changeable layer and an oxygen reservoir layer is provided. The first electrode is located on the substrate. The second electrode is located between the first electrode and the substrate. The resistance changeable layer is located between the first electrode and the second electrode. The oxygen reservoir layer is located between the first electrode and the resistance changeable layer. The oxygen reservoir layer includes a first portion, a second portion and a third portion. The second portion is connected to one side of the first portion. The third portion is connected to the other side of the first portion. A thickness of the first portion is greater than a thickness of the second portion and a thickness of the third portion. The first portion of the oxygen reservoir layer protrudes toward the first electrode.
    Type: Application
    Filed: May 25, 2021
    Publication date: June 2, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo
  • Publication number: 20220069210
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first dielectric layer, a bottom electrode, a resistance switching layer, an oxygen exchange layer, a barrier layer and a top electrode. The first dielectric layer is disposed on the substrate. The bottom electrode is disposed on the first dielectric layer. The resistance switching layer is disposed on the bottom electrode. The oxygen exchange layer is disposed on the resistance switching layer. A contact area between the oxygen exchange layer and the resistance switching layer is smaller than a top surface area of the resistance switching layer. The barrier layer is disposed on the oxygen exchange layer. The top electrode is disposed on the barrier layer.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Inventors: Po-Yen HSU, Bo-Lun WU, Tse-Mian KUO
  • Publication number: 20220005868
    Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Shih-Ning Tsai, Bo-Lun Wu, Tse-Mian Kuo
  • Patent number: 10840382
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 17, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chu-Chun Hsieh, Tse-Mian Kuo