Patents by Inventor Tsiu C. Chan

Tsiu C. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4392210
    Abstract: An integrated circuit memory cell pair having its data lines insulatively disposed from the semiconductor substrate at all points other than the point of electrical contact to the transistors of each memory cell. The semiconductor substrate has drain and source regions about the transmission channel of the field effect transistor and has a first capacitor electrode integral with one terminal of the transistor. A first polysilicon layer insulatively disposed from the substrate provides a conductive layer for a second capacitor electrode for each memory cell. A second insulatively disposed polysilicon layer provides the gate regions of the transistors and the data lines. The data lines make electrical contact through a self-aligned buried contact. Using this construction, a highly dense memory cell array is achieved without sacrificing capacitor area.
    Type: Grant
    Filed: August 28, 1978
    Date of Patent: July 5, 1983
    Assignee: Mostek Corporation
    Inventor: Tsiu C. Chan
  • Patent number: 4297721
    Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.
    Type: Grant
    Filed: May 29, 1979
    Date of Patent: October 27, 1981
    Assignee: Mostek Corporation
    Inventors: Vernon C. McKenny, Tsiu C. Chan
  • Patent number: 4290185
    Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.
    Type: Grant
    Filed: May 29, 1979
    Date of Patent: September 22, 1981
    Assignee: Mostek Corporation
    Inventors: Vernon G. McKenny, Tsiu C. Chan
  • Patent number: 4251876
    Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.
    Type: Grant
    Filed: November 3, 1978
    Date of Patent: February 17, 1981
    Assignee: Mostek Corporation
    Inventors: Vernon G. McKenny, Tsiu C. Chan
  • Patent number: 4125854
    Abstract: A symmetrical structural layout for the principal components of each cell in a group of four mutually contiguous cells of an array of memory cells is disclosed. A common drain supply node is centrally disposed within the group and is coincident with the intersection of first and second mutually perpendicular axes of symmetry. Corresponding components of contiguous cells in each row and column are symmetrically disposed with respect to each of the first and second axes of symmetry. In a preferred embodiment, the principal components of each cell include a plurality of insulated gate field-effect transistors each having a source diffusion region and a drain diffusion region formed within the substrate and a plurality of impedance devices electrically connecting the common drain supply node to the drain diffusions of the transistors in each cell.
    Type: Grant
    Filed: December 2, 1976
    Date of Patent: November 14, 1978
    Assignee: Mostek Corporation
    Inventors: Vernon G. McKenny, Tsiu C. Chan