Abstract: A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern.

Abstract: A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

Abstract: An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.

Abstract: A method of forming high contrast alignment marks on an integrated circuit wafer for patterning a layer of highly reflective electrode metal is described. A method of patterning a layer of highly reflective metal on an integrated circuit wafer using high contrast alignment marks is also described. Due to a difference in height of alignment marks and contact metal surrounding the alignment marks the alignment marks are transferred to the contour of the highly reflective electrode metal. A non reflective layer of bottom anti-reflection coating material is then used to provide high contrast at the location where the edges of the alignment marks are transferred to the highly reflective electrode metal.

Abstract: A method for forming a Spin-On-Glass (SOG) residue free Inter-Metal Dielectric (IMD) spacer layer as a substrate layer for a void free conformal insulator layer within a high aspect ratio exceedingly narrowly spaced patterned layer within an integrated circuit. First there is provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a first aperture formed therein. Formed upon the patterned layer and into the first aperture is a conformal Inter-Metal Dielectric (IMD) layer. The conformal Inter-Metal Dielectric (IMD) layer has a second aperture formed therein where the conformal Inter-Metal Dielectric (IMD) layer is formed into the first aperture. Formed upon the conformal Inter-Metal Dielectric (IMD) layer and filling the second aperture is a planarizing Spin-On-Glass (SOG) layer.

Abstract: An improved integrated circuit device with a reduced metal edge step height at the scribe line region edge and improved anti-reflection coating integrity is produced. This is accomplished by modification of the requisite photomask patterns used in circuit manufacture to provide an opaque region where the scribe line region is to be located, and an additional photomask pattern and photolithographic process to be employed after final metallization to render the scribe line region free of metallic or other material for eventual clean separation of the circuit die.

Abstract: Using an APM solution to clean both the front and backside of a semiconductor wafer significantly reduces the residue from chemical mechanical polishing. A low residue count holds the wafer more securely to the electrostatic chuck, thus improving processing, reducing wear on the electrostatic chuck, and increasing its lifetime.

Abstract: A method to produce a contact or via opening and filled metallurgy for CMOS or other integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer structure is formed thereover comprising a first layer of tetraethoxysilane (TEOS), a second layer of borophospho-TEOS (BPTEOS), and a third layer of TEOS. A contact opening is etched through the insulating layer structure not covered by a mask to the semiconductor device structures to be electrically contacted wherein the profile of the contact opening is not vertical because the BPTEOS layer is etched. horizontally more than the first and third TEOS layers and wherein native oxide builds up on the sidewalls of the contact opening.

Abstract: A method for the fabrication of an ohmic, low resistance contact to silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for a glass insulator layer deposited on the silicon. After the glass is flowed to planarize its surface, contact holes are patterned in the glass exposing the silicon substrate. The Ti/TiN barrier metallurgy is deposited by sputtering which, because of inferior edge coverage, results in a sidewall with a negative taper. Subsequent deposition of the tungsten results in a tungsten plug with an exposed void. The method taught by this invention deposits first a thin layer of tungsten whose thickness is governed by the amount of overhang caused by the tapered sidewall. An anisotropic dry etch step is then performed to achieve a vertical sidewall of tungsten. The remaining tungsten is then deposited to fill the contact opening without the occurrence of voids.

Abstract: This invention provides a method for removing metal etch residue of silicon nodules, resulting from a small percentage of silicon in the metal, without causing overetch damage to the photoresist pattern, the metal electrode pattern, or to dielectric layers. The metal conductor layer is partially etched leaving from 20 to 80 percent of the original thickness. Any residue of silicon nodules formed during this partial etching is then removed using ion bombardment. The remainder of the metal conductor layer is then etched. A short overetch period is used to remove any remaining residue of silicon nodules. The overetch period is short and there is no deterioration of the photoresist or exposed edges of the electrode pattern.

Abstract: A stilt includes a tube having a number of holes, and a sleeve is slidably engaged on the tube. The sleeve includes an orifice and a depression formed in a wall member for slidably receiving a catch and a spring. A lever is pivotally coupled to the sleeve and has one end engaged with the catch for moving the catch. A foot support is pivotally coupled to the sleeve. The spring biases the lever in order to engage the catch with either of the holes of the tube such that the sleeve may be adjusted along the tube when the catch is disengaged from the tube.