Abstract: An information processing apparatus includes in its body at least a power supply unit, a disk type storage and a printed circuit board arranged in a predetermined order and further has a keyboard unit which can be sandwiched between the display unit and a keyboard unit supporting portion extending from the body by pivotally moving the display unit. A detector for detecting the detachment of the keyboard unit from the body may be provided to restrict the range of pivotal movement of the display unit in accordance with a detection signal of the detector. Further, the display unit may be provided with pilot light emitting portions, thereby making it possible to recognize a condition of the information processing apparatus.

Abstract: An information processing apparatus having a work suspend/resume function which allows operator to use a main memory shared by different processings even when work suspension information is saved therein. A system for allowing a same operational environment as that set up in one information processing apparatus to be easily implemented in another information processing apparatus. A main memory used by a CPU for execution of processings has a function for storing information concerning the state of the information processing apparatus prevailing at a time point when execution of a given processing is suspended by a CPU for allowing the suspended processing to be performed in continuation later on. When the suspension state information has already been stored in the main memory by a former user, the suspension state information is transferred to a removable nonvolatile storage device so that the CPU can perform other processing than the suspended one by using the main memory.

Abstract: A data processing apparatus which includes a display unit and a power supply controller for supplying power to the display unit. The display unit has a display screen and a back light controller. The power supply controller comprises a switch, at least one output line for receiving the power from the switch and for supplying therethrough the power to electronic devices, a delay circuit for receiving the power from the switch and when the switch is turned ON to start supply of the power, for outputting the power after passage of a predetermined time from the start of the power supply, and a second output line for supplying the power from the delay circuit to the back light controller therethrough.

Abstract: A data reproducing circuit having a magnetic head for reading data from a recording medium, an adaptive equalization circuit for optimizing the waveform of a read signal, a discriminator circuit for discriminating an output signal of the adaptive equalization circuit and outputting a discriminated signal to an upper stage circuit, a format detecting circuit for detecting a pattern of signals written on the recording medium from outputs of the magnetic head, an expected value generating circuit for generating an expected value of the waveform of the read signal in accordance with an output of the adaptive equalization circuit and an output of the discriminator circuit, and an error detecting circuit for generating an error signal representing a difference between an output of the adaptive equalization circuit and an output of the expected value generating circuit.

Abstract: A data converting system converts CRT display data into display data for another display unit such as a liquid crystal display unit by use of a memory. The system includes a data load controller which selects one segment of data out of two segments of data in the CRT display data successively while changing the segment position to be selected alternately in every two frame scanning periods so that the CRT display data for one complete picture is written into the memory in two frame scanning periods, i.e., a segment is written into the memory once for every two adjacent segments. Display data is read out of the memory in the data form conformable to the other display unit.

Abstract: A one-dimensional image sensor comprising a solid image pick-up element takes images in sequence, and generates an image signal. Clock pulses from a frequency variable type clock pulse generator having a frequency which varies in correspondence to a control signal are supplied to a one-dimensional image sensor, thereby image signals are outputted in sequence. The image signal is amplified by an amplifier and inputted to a comparator and compared with a reference signal. A frequency variable range of the frequency variable type clock pulse generator is set higher than the cut-off frequency of the amplifier, and the binary level output by the comparator is substantially the same as the image inputted to the one-dimensional image sensor and control is effected by the variable frequency of the clock pulses.

Abstract: A liquid crystal display is capable of displaying intermediate, partial or half tones of images, while at the same time preventing the occurrence of flicker and the decay of the liquid crystal panel. The display operation for data to be displayed in an intermediate tone has one or more lines of a repeating frame of display data that are prohibited from being displayed during in each frame. Such inhibited display lines are designated differently on a sequential basis over consecutive frames, and the sequence of designation is varied in successive frames in accord with changing patterns.

Abstract: In accordance with the present invention, there is provided a data processing apparatus comprising an MPU which inputs or outputs an address signal and a data signal on the time sharing basis, a latching means for latching said address signal, a memory which must be refreshed, and changeover means for connecting said memory to said MPU during a data signal period and connecting said memory to a refresh counter during remaining periods.

Abstract: A data transfer system comprises data retaining means for retaining n-bit digital data (n being an integer), serial/parallel data converting means for converting the n-bit digital data transferred from the data retaining means from parallel data to serial data or vice versa in synchronism with first clock signals generated at a first clock frequency, counting means for counting second clock signals generated at a second clock frequency, and control means for transferring the n-bit digital data from the data retaining means to the serial/parallel data converting means each time the counting means counts a predetermined number of clock signals.

Abstract: A data processing system has a dynamic type memory, a static type memory for storing data periodically read out, a central processing unit for transferring data to and from the two memories, an address generating circuit for periodically applying an address to the static type memory to read out the contents thereof, and an address selecting unit for exclusively selecting an address from the central processing unit or an address from the address generating circuit. In the system, the two memories are connected to the address selecting unit in order that the address selected by the address selecting means is supplied common to both the memories.

Abstract: A display apparatus for use with a cathode-ray tube capable of displaying patterns in interlaced scanning and non-interlaced scanning operation modes, comprising a composite video signal synthesizer, a memory for storing pattern data, a mode setting circuit for the memory, a data selection signal generator and a raster line number signal generator. The memory stores data for relatively simple patterns such as alphabetical letters and those for relatively complicated patterns such as Chinese characters in individually particular areas in the memory addresses of these different areas are identified by a combination of the data selection signal and the raster line number signal supplied to the memory from the data selection signal generator and the raster line number signal generator. Accordingly, the apparatus is capable of displaying both relatively simple and relatively complicated patterns with satisfactory resolution and with a relatively small-scale structure.

Abstract: In a display signal generating means in a display device for both the character display and the graphic display, address conversion means is provided for converting the addresses of one character in a plurality of lines of one character section of a memory field corresponding to a display panel into a predetermined address or addresses.

Abstract: In a .phi..sub.2 cycle steal mode, a clock signal is selected such that a time period during which a RAM is connected to a timing signal generator for display is extended and a time period during which the RAM is connected to a CPU is shortened accordingly, without changing an overall period. This clock signal is used to actuate a switching circuit for the RAM while a clock signal having unmodified duty ratio is applied to the CPU, a ROM and external circuits so that a display data readout period from the RAM is extended without affecting the CPU clock frequency and the operation of other circuits. During this readout period, a plurality of display address signals are applied to the RAM from the timing signal generator and a plurality of data derived from the RAM are sequentially loaded in a register which is then read out at a desired timing to enable the display of a plurality of characters in one CPU clock period.

Abstract: A memory selection system which facilitates the addition of an external memory to a digital processing unit having an internal memory is disclosed. When a plurality of memories have the same addresses and an overlapped address is accessed, priority among the memories having the overlapped address is discriminated to enable only the memory having the highest priority (last attached memory) to be selected for access and to disable the access of the other memories.

Abstract: A digital data processing device in which a color memory has a temporal data storage register at input/output interface thereof so that the data write-in or data read-out operations executed by a micro-processing unit (MPU) is always performed through the temporal storage register. When data read-out or write-in operation is made to a character memory at a certain address, the same operation is simultaneously carried out for the color memory at the corresponding address. Assuming that MPU reads out a certain display address of a display screen, a corresponding character code is fetched by MPU from the character memory, while the corresponding color code is transferred to the temporal storage register from the color memory. When MPU performs the write-in operation for another address of the display screen, the character code held by MPU until then is written in the character memory at a designated address, while the color data i.e.

Abstract: A data processing system such as a character display system is provided with a first memory circuit for storing coded characters to be displayed, a second memory circuit for storing picture element information of characters to be displayed, and a character display drive circuit for extracting the coded character information from said first memory circuit and extracting and reproducing the picture element information from said second memory circuit. The first memory circuit includes a plurality of random access memories (RAMs). The character display system further includes an address switching circuit for successively and alternately applying an address signal from the character display drive circuit to the RAMs, and an output signal switching circuit for switching the information output signals extracted from the RAMs in synchronism with the switching operation of the address switching circuit.

Abstract: A liquid crystal display is capable of displaying intermediate, partial or half tones of images, while at the same time preventing the occurrence of flicker and the decay of the liquid crystal panel. The display operation for data to be displayed in an intermediate tone has one or more lines of a repeating frame of display data that are prohibited from being displayed during in each frame. Such inhibited display lines are designated differently on a sequential basis over consecutive frames, and the sequence of designation is varied in successive frames in accord with changing patterns.