Patents by Inventor Tsunehiro Ino
Tsunehiro Ino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200303382Abstract: A semiconductor memory device includes: a first and a second electrodes aligned in a first direction; a first semiconductor layer provided between the first and the second electrodes; a second semiconductor layer provided between the first semiconductor layer and the second electrode; a first charge accumulating layer provided between the first electrode and the first semiconductor layer; and a second charge accumulating layer provided between the second electrode and the second semiconductor layer. At least one of the first and the second charge accumulating layers include: a first and a second regions including nitrogen, aluminum, and oxygen and having different positions in a second direction; and a third region provided between the first and the second regions in the second direction. Oxygen is not included in the third region or a concentration of oxygen in the third region is lower than that in the first and the second regions.Type: ApplicationFiled: September 9, 2019Publication date: September 24, 2020Applicant: Toshiba Memory CorporationInventors: Akira TAKASHIMA, Tsunehiro INO, Ayaka SUKO
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Publication number: 20200227108Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Applicant: Toshiba Memory CorporationInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Patent number: 10636468Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: GrantFiled: August 27, 2018Date of Patent: April 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Publication number: 20200091160Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, and a first layer provided between the first conductive layer and the second conductive layer and containing aluminum oxide that contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide is a ferroelectric.Type: ApplicationFiled: March 21, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yuuichi KAMIMUTA
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Publication number: 20200066868Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Patent number: 10510862Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: GrantFiled: September 18, 2018Date of Patent: December 17, 2019Assignee: Toshiba Memory CorporationInventors: Tsunehiro Ino, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Publication number: 20190319043Abstract: According to one embodiment, a semiconductor memory device includes a first conductive member, a first semiconductor member, and a first stacked member provided between the first conductive member and the first semiconductor member. The first stacked member includes a first insulating film, a second insulating film provided between the first insulating film and the first semiconductor member, first and second layers. The first layer includes aluminum and nitrogen and is provided between the first and second insulating films. A first thickness of the first layer along a first direction is 3 nm or less. The first direction is from the first semiconductor member toward the first conductive member. The second layer contacts the first layer, includes silicon and nitrogen, and is provided at one of a position between the first layer and the second insulating film or a position between the first layer and the first insulating film.Type: ApplicationFiled: March 12, 2019Publication date: October 17, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akira TAKASHIMA, Tsunehiro INO, Yuuichi KAMIMUTA, Ayaka SUKO
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Publication number: 20190296122Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.Type: ApplicationFiled: September 18, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Tsunehiro INO, Yusuke Higashi, Toshinori Numata, Yuuichi Kamimuta
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Publication number: 20190287599Abstract: A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.Type: ApplicationFiled: August 27, 2018Publication date: September 19, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Higashi, Yuuichi Kamimuta, Tsunehiro Ino
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Patent number: 10403815Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric film or a ferrielectric film provided between the first conductive layer and the second conductive layer, the ferroelectric film or the ferrielectric film including hafnium oxide containing at least one first element selected from Zn, Mg, Mn, Nb, Sc, Fe, Cr, Co, In, Li and N.Type: GrantFiled: September 3, 2015Date of Patent: September 3, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tsunehiro Ino
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Patent number: 10096619Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.Type: GrantFiled: September 6, 2016Date of Patent: October 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsunehiro Ino, Shosuke Fujii, Seiji Inumiya
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Patent number: 9935122Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.Type: GrantFiled: March 16, 2016Date of Patent: April 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsunehiro Ino, Daisuke Matsushita, Yasushi Nakasaki, Misako Morota, Akira Takashima, Kenichiro Toratani
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Patent number: 9779797Abstract: A non-volatile memory device according to an embodiment includes a first conductive layer, a second conductive layer including metal nitride, the metal nitride absorbing oxygen, a paraelectric layer disposed between the first conductive layer and the second conductive layer, a ferroelectric layer disposed between the paraelectric layer and the second conductive layer, the ferroelectric layer including hafnium oxide, at least one third conductive layer disposed on opposite side of at least one of the first conductive layer and the second conductive layer to the ferroelectric layer, the at least one third conductive layer including metal oxide, the metal oxide having oxygen ratio larger than stoichiometric ratio, and a sense circuit configured to read data based on tunneling current flow between the first conductive layer and the second conductive layer through the paraelectric layer and the ferroelectric layer.Type: GrantFiled: August 24, 2016Date of Patent: October 3, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsunehiro Ino, Shosuke Fujii
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Publication number: 20170271466Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.Type: ApplicationFiled: September 15, 2016Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daisuke MATSUSHITA, Yasushi NAKASAKI, Tsunehiro INO
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Patent number: 9768265Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.Type: GrantFiled: September 15, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Daisuke Matsushita, Yasushi Nakasaki, Tsunehiro Ino
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Patent number: 9691973Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.Type: GrantFiled: September 2, 2015Date of Patent: June 27, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Riichiro Takaishi, Koichi Kato, Yasushi Nakasaki, Takamitsu Ishihara, Daisuke Matsushita
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Patent number: 9634248Abstract: According to one embodiment, an insulator includes a material including barium and hafnium oxide. The material has a crystal structure of a space group Pbc21.Type: GrantFiled: March 4, 2016Date of Patent: April 25, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Yasushi Nakasaki, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20170077115Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.Type: ApplicationFiled: March 16, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Daisuke MATSUSHITA, Yasushi NAKASAKI, Misako MOROTA, Akira TAKASHIMA, Kenichiro TORATANI
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Publication number: 20170069841Abstract: According to one embodiment, an insulator includes a material including barium and hafnium oxide. The material has a crystal structure of a space group Pbc21.Type: ApplicationFiled: March 4, 2016Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Yasushi NAKASAKI, Shosuke FUJII, Daisuke MATSUSHITA
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Publication number: 20160372478Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.Type: ApplicationFiled: September 6, 2016Publication date: December 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Shosuke FUJII, Seiji INUMIYA