Patents by Inventor Tsuneo Ogura
Tsuneo Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130082302Abstract: A semiconductor device comprises: a substrate having a first and second surface; trenches provided on the second surface; a gate electrode provided in each trench; a first-conductive-type emitter layer provided on the second surface and contacting with the trenches; and an emitter electrode provided on the second surface to extend in a longitudinal direction of the trenches, the emitter electrode having a non-contact portion partially provided in the first-conductive-type emitter layer.Type: ApplicationFiled: September 12, 2012Publication date: April 4, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Kazutoshi NAKAMURA, Tsuneo Ogura
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Patent number: 8319314Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and tType: GrantFiled: January 13, 2011Date of Patent: November 27, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Masakazu Yamaguchi, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Patent number: 8217420Abstract: According to one embodiment, a power semiconductor device includes an IGBT region, first and second electrodes, and a first conductivity-type second semiconductor layer. The region functions as an IGBT element. The first electrode is formed in a surface of a second conductivity-type collector layer opposite to a first conductivity-type first semiconductor layer in the region. The second electrode is connected onto a first conductivity-type emitter layer and a second conductivity-type base layer in a surface of the first conductivity-type base layer and insulated from a gate electrode in the region. The first conductivity-type second semiconductor layer extends from the surface of the first conductivity-type base layer to the first conductivity-type first semiconductor layer around the IGBT region, and connected to the first electrode.Type: GrantFiled: August 6, 2010Date of Patent: July 10, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Tsuneo Ogura
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Publication number: 20120074459Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer.Type: ApplicationFiled: September 15, 2011Publication date: March 29, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Tsuneo OGURA
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Publication number: 20120061724Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.Type: ApplicationFiled: September 14, 2011Publication date: March 15, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Tsuneo OGURA
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Publication number: 20110101417Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and tType: ApplicationFiled: January 13, 2011Publication date: May 5, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo OGURA, Masakazu Yamaguchi, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Patent number: 7915617Abstract: A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.Type: GrantFiled: July 3, 2006Date of Patent: March 29, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Ichiro Omura
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Publication number: 20110042714Abstract: According to one embodiment, a power semiconductor device includes an IGBT region, first and second electrodes, and a first-conductivity-type second semiconductor layer. The region functions as an IGBT element. The first electrode is formed in a surface of a second-conductivity-type collector layer opposite to a first-conductivity-type first semiconductor layer in the region. The second electrode is connected onto a first-conductivity-type emitter layer and a second-conductivity-type base layer in a surface of the first-conductivity-type base layer and insulated from a gate electrode in the region. The first-conductivity-type second semiconductor layer extends from the surface of the first-conductivity-type base layer to the first-conductivity-type first semiconductor layer around the IGBT region, and connected to the first electrode.Type: ApplicationFiled: August 6, 2010Publication date: February 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tsuneo OGURA
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Patent number: 7800168Abstract: A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.Type: GrantFiled: August 3, 2007Date of Patent: September 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Patent number: 7781869Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.Type: GrantFiled: August 4, 2006Date of Patent: August 24, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoki Inoue, Koichi Sugiyama, Hideaki Ninomiya, Tsuneo Ogura
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Patent number: 7772641Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.Type: GrantFiled: March 6, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
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Patent number: 7531871Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.Type: GrantFiled: December 5, 2005Date of Patent: May 12, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
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Publication number: 20090039386Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and tType: ApplicationFiled: October 10, 2008Publication date: February 12, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo OGURA, Masakazu Yamaguchi, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Patent number: 7456487Abstract: This disclosure concerns a semiconductor device that includes a first base layer; second base layers provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers; an emitter layer formed on a surface of the second base layers; a collector layer provided below a second surface of the first base layer, an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being electrically isolated from the emitter layer and the second base layers, wherein the space section includes a semiconductor layer being deeper than the second base layers.Type: GrantFiled: October 28, 2004Date of Patent: November 25, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Masakazu Yamaguchi, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Publication number: 20070278566Abstract: A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.Type: ApplicationFiled: August 3, 2007Publication date: December 6, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Patent number: 7294886Abstract: Disclosed is a power semiconductor device, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are alternately and laterally arranged on the first semiconductor layer and, a fourth semiconductor layer of the second conductivity type selectively formed in the surface regions of the second and third semiconductor layers, a fifth semiconductor layer of the first conductivity type selectively formed in the surface region of the fourth semiconductor layer, and a control electrode formed on the surfaces of the second, fourth and fifth semiconductor layers, in which a layer thickness ratio A is given by the expression: 0<A=t/(t+d)?0.72 where t is the thickness of the first semiconductor layer, and d is the thickness of the second semiconductor layer.Type: GrantFiled: November 3, 2005Date of Patent: November 13, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Ichiro Omura, Tsuneo Ogura
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Publication number: 20070210350Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.Type: ApplicationFiled: March 6, 2007Publication date: September 13, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
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Patent number: 7268390Abstract: A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.Type: GrantFiled: April 11, 2005Date of Patent: September 11, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Publication number: 20070007537Abstract: A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.Type: ApplicationFiled: July 3, 2006Publication date: January 11, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Ichiro Omura
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Publication number: 20060267129Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.Type: ApplicationFiled: August 4, 2006Publication date: November 30, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Tomoki Inoue, Koichi Sugiyama, Hideaki Ninomiya, Tsuneo Ogura