Patents by Inventor Tsung-Ching Wu

Tsung-Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148166
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Application
    Filed: August 1, 2018
    Publication date: May 16, 2019
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Publication number: 20190146316
    Abstract: A wavelength conversion device includes a main body, at least one wavelength conversion layer, at least one heat dissipation plate, a heat conducting component and a driving unit. The wavelength conversion layer is disposed on the main body. The heat dissipation plate is disposed on a side of the main body with an interval. The heat conducting component is connected between the heat dissipation plate and the main body. The driving unit is connected to the main body and the heat dissipation plate and adapted to drive the main body and the heat dissipation plate to rotate. The driving unit and the heat conducting component have a gap therebetween. In addition, a projector including the wavelength conversion device is also provided. The wavelength conversion device according to the disclosure has good heat dissipation efficiency.
    Type: Application
    Filed: November 12, 2018
    Publication date: May 16, 2019
    Applicant: Coretronic Corporation
    Inventors: Te-Ying Tsai, Tsung-Ching Lin, Shi-Wen Lin, Pei-Rong Wu, Chia-Lun Tsai
  • Patent number: 9595335
    Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 14, 2017
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern, Steven Schumann, Philip S. Ng
  • Publication number: 20160005477
    Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.
    Type: Application
    Filed: September 18, 2015
    Publication date: January 7, 2016
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern, Steven Schumann, Philip S. Ng
  • Patent number: 9142306
    Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: September 22, 2015
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern, Steven Schumann, Philip S. Ng
  • Patent number: 8946574
    Abstract: In one embodiment, an method apparatus includes an optically clear adhesive (OCA) layer between a cover sheet and a substrate. The substrate has drive or sense electrodes of a touch sensor disposed on a first surface and a second surface of the substrate. The first surface is opposite the second surface and the drive or sense electrodes are made of a conductive mesh of conductive material including metal.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 3, 2015
    Assignee: Atmel Corporation
    Inventors: David Brent Guard, Esat Yilmaz, Tsung-Ching Wu
  • Patent number: 8797285
    Abstract: An electrode pattern for a position sensing panel may have an array of mesh cells formed by sinusoidaly shaped conductive lines extending between vertices of the mesh cells.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: August 5, 2014
    Assignee: Atmel Corporation
    Inventors: David Brent Guard, Esat Yilmaz, Tsung-Ching Wu
  • Publication number: 20140198571
    Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.
    Type: Application
    Filed: June 19, 2013
    Publication date: July 17, 2014
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern, Steven Schumann, Philip S. Ng
  • Publication number: 20140132523
    Abstract: In one embodiment, a method performed by executing logic embodied by one or more computer-readable non-transitory storage media includes sending a first signal on a first line of a touch sensor. The first line includes a first plurality of electrodes. The method includes receiving a reflection of the first signal on the first line of the touch sensor. The method also includes determining coordinates of a touch on a device comprising the touch sensor in response to receiving the reflection of the first signal.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Inventors: David Brent Guard, Tsung-Ching Wu, Esat Yilmaz
  • Publication number: 20120262382
    Abstract: An electrode pattern for a position sensing panel may have an array of mesh cells formed by sinusoidaly shaped conductive lines extending between vertices of the mesh cells.
    Type: Application
    Filed: April 18, 2011
    Publication date: October 18, 2012
    Inventors: David Brent Guard, Esat Yilmaz, Tsung-Ching Wu
  • Publication number: 20120261242
    Abstract: In one embodiment, an method apparatus includes an optically clear adhesive (OCA) layer between a cover sheet and a substrate. The substrate has drive or sense electrodes of a touch sensor disposed on a first surface and a second surface of the substrate. The first surface is opposite the second surface and the drive or sense electrodes are made of a conductive mesh of conductive material including metal.
    Type: Application
    Filed: December 6, 2011
    Publication date: October 18, 2012
    Inventors: David Brent Guard, Esat Yilmaz, Tsung-Ching Wu
  • Publication number: 20120262412
    Abstract: In one embodiment, a touch sensor includes one or more meshes of conductive material. Each of the meshes includes a plurality of conductive lines. A first one of the conductive lines has a first portion and a second portion. The first portion is wider than the second portion.
    Type: Application
    Filed: January 11, 2012
    Publication date: October 18, 2012
    Inventors: David Brent Guard, Esat Yilmaz, Tsung-Ching Wu
  • Patent number: 7848151
    Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: December 7, 2010
    Assignee: Atmel Corporation
    Inventors: Johnny Chan, Philip S. Ng, Alan L. Renninger, Jinshu Son, Jeffrey M. Tsai, Tin-Wai Wong, Tsung-Ching Wu
  • Publication number: 20090168586
    Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 2, 2009
    Applicant: Atmel Corporation
    Inventors: Johnny Chan, Philip S. Ng, Alan L. Renninger, Jinshu Son, Jeffrey Ming-Hung Tsai, Tin-Wai Wong, Tsung-Ching Wu
  • Patent number: 7512008
    Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: March 31, 2009
    Assignee: Atmel Corporation
    Inventors: Johnny Chan, Philip S. Ng, Alan L. Renninger, Jinshu Son, Jeffrey Ming-Hung Tsai, Tin-Wai Wong, Tsung-Ching Wu
  • Publication number: 20070121382
    Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
    Type: Application
    Filed: November 30, 2005
    Publication date: May 31, 2007
    Inventors: Johnny Chan, Philip Ng, Alan Renninger, Jinshu Son, Jeffrey Tsai, Tin-Wai Wong, Tsung-Ching Wu
  • Patent number: 5434815
    Abstract: Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective for grounding the gate of a variable threshold programmable transistor in the memory cell. Power down of the word line is reflected in synchronous power-down of the sense line. Additionally, with power down, the sense amplifier for the particular core memory cell is disconnected from a master latch circuit, which in turn is connected to a slave latch circuit for applying the previous sense amplifier output to an input/output buffer, in order to secure the data sensed in core memory during read operation. The invention further permits reduced word line voltages during erase operation on the sense line and the variable threshold programmable transistor.
    Type: Grant
    Filed: January 19, 1994
    Date of Patent: July 18, 1995
    Assignee: Atmel Corporation
    Inventors: George Smarandoiu, Steven J. Schumann, Tsung-Ching Wu
  • Patent number: 5081054
    Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.
    Type: Grant
    Filed: February 5, 1991
    Date of Patent: January 14, 1992
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern
  • Patent number: 5066992
    Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.
    Type: Grant
    Filed: October 29, 1990
    Date of Patent: November 19, 1991
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern
  • Patent number: RE35094
    Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: November 21, 1995
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern