Patents by Inventor Tsung-Ching Wu

Tsung-Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4970565
    Abstract: A memory cell in an EPROM device which is totally sealed from ultraviolet light by a conductive cover without openings therein for leads to the cell's drain, source and gate. Electrical communication with the source is provided by direct contact with the conductive cover. Access to the drain and floating gate is provided by buried N+ implants, buried N+ layers or N-wells crossing underneath the sides of the cover. The memory cell has a single poly floating gate rather than a stacked floating gate/control gate combination. The buried N+ implant or N-well serves as the control gate and is capacitvely coupled to the floating gate via a thin oxide layer in a coupling area.
    Type: Grant
    Filed: May 10, 1990
    Date of Patent: November 13, 1990
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, James C. Hu, John Y. Huang
  • Patent number: 4859619
    Abstract: A process of fabricating high performance EPROMs in which memory cell devices and high voltage circuit devices are formed in p-type tub regions of high threshold voltage. The tub regions are formed by implanting boron ions in photolithographically defined memory cell and high voltage device areas of a p-type wafer substrate, then subjecting the substrate to a high temperature drive-in. The N-channel isolation field is formed separately and has a lower threshold voltage than the tub regions. The isolation field is formed by implanting boron ions around all device areas, including low voltage device areas, using a nitride mask and a low implantation energy. The wafer is then subjected to an anneal step followed by a field oxidation step. The memory cell and other MOS devices are finally formed in the appropriate defined regions.
    Type: Grant
    Filed: July 15, 1988
    Date of Patent: August 22, 1989
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern, James C. Hu
  • Patent number: 4822750
    Abstract: A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.
    Type: Grant
    Filed: July 16, 1987
    Date of Patent: April 18, 1989
    Assignee: Seeq Technology, Inc.
    Inventors: Gust Perlegos, Tsung-Ching Wu
  • Patent number: 4701776
    Abstract: A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.
    Type: Grant
    Filed: December 1, 1986
    Date of Patent: October 20, 1987
    Assignee: Seeq Technology, Inc.
    Inventors: Gust Perlegos, Tsung-Ching Wu