Patents by Inventor Tsung-Hsien Tsai

Tsung-Hsien Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11211936
    Abstract: Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Tsai, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20210375783
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Application
    Filed: July 16, 2020
    Publication date: December 2, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Publication number: 20210336613
    Abstract: A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.
    Type: Application
    Filed: February 18, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Tsung-Hsien Tsai
  • Publication number: 20210270879
    Abstract: Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.
    Type: Application
    Filed: December 17, 2020
    Publication date: September 2, 2021
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20210265058
    Abstract: A training data processing method and an electronic device are provided. The method includes: obtaining medical history data including at least one first disease suffered by a user; setting a plurality of disease types according to a target disease; setting a time interval; obtaining at least one second disease in the time interval from the medical history data; performing a pre-processing operation on the second disease according to the disease types to obtain processed data; and inputting the processed data to a neural network to train the neural network.
    Type: Application
    Filed: April 9, 2020
    Publication date: August 26, 2021
    Applicants: Acer Incorporated, National Yang-Ming University
    Inventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Li-Ning Peng, Fei-Yuan Hsiao, Shih-Tsung Huang
  • Publication number: 20210258003
    Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
  • Publication number: 20210242862
    Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
  • Publication number: 20210226584
    Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.
    Type: Application
    Filed: December 14, 2020
    Publication date: July 22, 2021
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 11069633
    Abstract: The disclosure provides an electronic package, including a carrier, an electronic component disposed on the carrier, a buffer, and an antenna structure, wherein the antenna structure includes a metal frame disposed on the carrier and a wire disposed on the carrier and electrically connected to the metal frame, and the buffer covers the wire so as to reduce the emission wave speed of the wire and thus the wavelength is shorten, thereby satisfying the length requirement of the antenna within the limited space of the carrier and achieving an operating frequency radiated as required.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 20, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ming-Fan Tsai, Chih-Hsien Chiu, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
  • Publication number: 20210209503
    Abstract: A method and an electronic device for selecting influence indicators by using an automatic mechanism are provided. The method includes following steps. Raw data is obtained, where the raw data includes a body-related variable and a plurality of to-be-measured indicators corresponding to the body-related variable. The body-related variable is set as a target parameter. The body-related variable and the to-be-measured indicators are input into a plurality of validation models, and the to-be-measured indicators are sorted according an output result of the validation models to obtain ranking data. Importance of the to-be-measured indicators is calculated by using a screening condition according to the ranking data, so as to select a candidate indicator from the to-be-measured indicators. An influence indicator is determined by calculating a correlation between the candidate indicator and the body-related variable.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 8, 2021
    Applicants: Acer Incorporated, National Yang-Ming University
    Inventors: Zong-Han Tsai, Tsung-Hsien Tsai, Liang-Kung Chen, Li-Ning Peng, Ting-Fen Tsai, Chi-Hung Lin, Chien-Yi Tung, Wei-Ju Lin
  • Publication number: 20210210435
    Abstract: An electronic package and a manufacturing method thereof are provided, where a plurality of shielding wires are arranged on a carrier and spanning across an electronic component to cover the electronic component, so that the shielding wires serve as a shielding structure to protect the electronic component from the interference of external electromagnetic waves.
    Type: Application
    Filed: August 19, 2020
    Publication date: July 8, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ming-Fan Tsai, Chih-Wei Chen, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
  • Patent number: 11031927
    Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
  • Publication number: 20210113158
    Abstract: A feature identifying method and an electronic device are provided. The method includes: obtaining a plurality of physiological information obtained by measuring a subject at a plurality of time points in one day; converting the plurality of physiological information into a plurality of correlation features respectively; establishing a plurality of first risk prediction models according to the plurality of correlation features, and identifying at least one first correlation feature from the plurality of correlation features according to the plurality of first risk prediction models; establishing a plurality of second risk prediction models according to the at least one first correlation feature, and identifying, according to the plurality of second risk prediction models, at least one second correlation feature capable of predicting a specific disease from the at least one first correlation feature; and outputting the at least one second correlation feature.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 22, 2021
    Applicants: Acer Incorporated, National Yang-Ming University
    Inventors: Chun-Hsien Li, Tsung-Hsien Tsai, Liang-Kung Chen, Chen-Huan Chen, Hao-Min Cheng
  • Patent number: 10958257
    Abstract: A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Tsung-Hsien Tsai
  • Patent number: 10948240
    Abstract: A vapor chamber structure includes a main body, a fan and perforations. The main body has a heat absorption section, a heat dissipation section and a chamber. The heat absorption section and the heat dissipation section are respectively horizontally disposed on left and right sides of the main body. The heat absorption section is attached to at least one heat source. The chamber is positioned at the heat absorption section and partially extends to the heat dissipation section. The chamber has a capillary structure and at least one perforated section. The perforated section is connected between an upper side and a lower side of the chamber. The fan is disposed on one side of the heat dissipation section. The perforations are formed through the parts of the main body, which parts are free from the chamber and the parts of the main body, where the perforated section is disposed.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: March 16, 2021
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Kuo-Chun Hsieh, Tsung-Hsien Tsai
  • Publication number: 20210028772
    Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.
    Type: Application
    Filed: October 8, 2020
    Publication date: January 28, 2021
    Inventors: Tsung-Hsien TSAI, Ruey-Bin SHEEN, Chih-Hsien CHANG, Cheng-Hsiang HSIEH
  • Publication number: 20200412351
    Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation is circuit configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
    Type: Application
    Filed: January 3, 2020
    Publication date: December 31, 2020
    Inventors: Ruey-Bin Sheen, Ming Hsien Tsai, Chih-Hsien Chang, Tsung-Hsien Tsai
  • Publication number: 20200402659
    Abstract: A disease suffering probability prediction method and an electronic apparatus are provided. The method includes: determining a path length; obtaining a plurality of first paths conforming to the path length from a plurality of history data of a specific disease; obtaining a plurality of second paths positively related to the specific disease from the plurality of first paths; filtering the plurality of second paths to obtain a plurality of third paths, and establishing a prediction model according to the plurality of third paths; and inputting a path to be predicted to the prediction model and outputting a probability of suffering the specific disease.
    Type: Application
    Filed: October 30, 2019
    Publication date: December 24, 2020
    Applicants: Acer Incorporated, National Yang-Ming University
    Inventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Li-Ning Peng
  • Patent number: 10868546
    Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10868496
    Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh