Patents by Inventor Tsung-Hsien Tsai

Tsung-Hsien Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741483
    Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 11, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen
  • Publication number: 20200242193
    Abstract: A statistical performance evaluation method for different grouping sets includes setting a plurality of first grouping ranges of a first grouping set corresponding to a sample space, setting a plurality of second grouping ranges of a second grouping set corresponding to the sample space, generating a plurality of first probability values and a plurality of first standard deviations corresponding to the plurality of first grouping ranges at each sampling time according to the sample space, generating a plurality of second probability values and a plurality of second standard deviations corresponding to the plurality of second grouping ranges at the each sampling time according to the sample space, and generating a plurality of statistical indicators corresponding to the first grouping set and the second grouping set and outputting a statistical performance ranking result of the first grouping set and the second grouping set accordingly.
    Type: Application
    Filed: May 23, 2019
    Publication date: July 30, 2020
    Inventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Li-Ning Peng, Wei-Ju Li
  • Patent number: 10720686
    Abstract: A novel miniaturized horizontal split-wave orthomode transducer includes a common channel portion, a first polarized channel portion and a second polarized channel portion, and the centers of the openings of the first polarized channel and the second polarized channel are coaxially and respectively arranged on two opposite sides of the common channel portion to save the bend and extended structure at the rear end of the horizontal split-wave orthomode transducer and also save the occupied space since there is no need to guide signals in one of the polarization directions to the rear and return the signals, so as to further achieve the effects of improving the flexibility of installing the transducer, providing a good isolation between electromagnetic signals in different polarization directions and preventing the interference occurred between the electromagnetic signals.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 21, 2020
    Inventors: Yu-Cheng Chen, Xuan-Wei Zhang, Jen-Ti Peng, Hsiu-Yun Liu, Wei-Chen Chien, Hsueh-Han Chen, Tsung-Hsien Tsai
  • Publication number: 20200219968
    Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Syu-Tang LIU, Huang-Hsien CHANG, Tsung-Tang TSAI, Hung-Jung TU
  • Patent number: 10700008
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hao-Yi Tsai, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 10680050
    Abstract: A display device is provided. The display device includes a substrate and an insulating layer disposed on the substrate and having a recess. The display device also includes an organic layer disposed on the insulating layer. The display device also includes at least one light emitting unit disposed in the recess and a conductive layer disposed on the light emitting unit.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 9, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Tsung-Han Tsai, Kuan-Feng Lee, Yu-Hsien Wu, Yuan-Lin Wu
  • Publication number: 20200176430
    Abstract: A display device is provided. The display device includes a supporting film and a flexible substrate disposed on the supporting film. The display device also includes a driving layer disposed on the flexible substrate, and a conductive pad disposed on the driving layer. The display device further includes a light-emitting diode disposed on the conductive pad and electrically connected to the conductive pad, wherein the supporting film has a first hardness, the flexible substrate has a second hardness, and the first hardness is greater than or equal to the second hardness.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Yuan-Lin WU, Yu-Hsien WU, Kuan-Feng LEE, Tsung-Han TSAI
  • Publication number: 20200161756
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 10643698
    Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: May 5, 2020
    Assignee: Windbond Electronics Corp.
    Inventors: Lih-Wei Lin, Ju-Chieh Cheng, Tsung-Huan Tsai, I-Hsien Tseng
  • Patent number: 10644869
    Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Chih-Hsien Chang
  • Publication number: 20200134504
    Abstract: A system of training behavior labeling model is provided. Specifically, a processing unit inputs each data of a training data set into a plurality of learning modules to establish a plurality of labeling models. The processing unit obtains a plurality of second labeling information corresponding to each data of a verification data set and generates a behavior labeling result according to the second labeling information corresponding to each data of the verification data set. The processing unit obtains a labeling change value according to the behavior labeling result and first labeling information corresponding to each data of the verification data set. The processing unit, if determining that the labeling change value is greater than a change threshold, updates the first labeling information according to the behavior labeling results, exchanges the training data set and the verification data set and reestablishes the labeling models.
    Type: Application
    Filed: February 26, 2019
    Publication date: April 30, 2020
    Applicant: Acer Cyber Security Incorporated
    Inventors: Chun-Hsien Li, Yin-Hsong Hsu, Chien-Hung Li, Tsung-Hsien Tsai, Chiung-Ying Huang, Ming-Kung Sun, Zong-Cyuan Jhang
  • Publication number: 20200127648
    Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Tsung-Hsien TSAI, Ruey-Bin SHEEN, Chih-Hsien CHANG, Cheng-Hsiang HSIEH
  • Publication number: 20200110689
    Abstract: A method for detecting abnormality adapted to detect abnormal operations of an operating system is provided. The method includes: calculating a safe range of usage of the operating system during one or more time periods according to a historical data stream; calculating abnormal ratios corresponding to the one or more time periods according to a current data stream and the safe range of usage; selecting one or more abnormal time periods from the one or more time periods according to a threshold and the abnormal ratios; calculating an abnormal indicator for each of the one or more abnormal time periods according to the historical data stream and the current data stream; and ranking the one or more abnormal time periods according to the abnormal indicator(s).
    Type: Application
    Filed: February 21, 2019
    Publication date: April 9, 2020
    Applicant: Acer Cyber Security Incorporated
    Inventors: Chun-Hsien Li, Chien-Hung Li, Jun-Mein Wu, Ming-Kung Sun, Zong-Cyuan Jhang, Yin-Hsong Hsu, Chiung-Ying Huang, Tsung-Hsien Tsai
  • Publication number: 20200105638
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: February 4, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200091919
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien TSAI, Chih-Hsien CHANG, Ruey-Bin SHEEN, Cheng-Hsiang HSIEH
  • Patent number: 10593657
    Abstract: A display device is provided. The display device includes a supporting film and a flexible substrate disposed on the supporting film. The display device also includes a driving layer disposed on the flexible substrate, and a conductive pad disposed on the driving layer. The display device further includes a light-emitting diode disposed on the conductive pad and electrically connected to the conductive pad, wherein the supporting film has a first hardness, the flexible substrate has a second hardness, and the first hardness is greater than or equal to the second hardness.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: March 17, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Yuan-Lin Wu, Yu-Hsien Wu, Kuan-Feng Lee, Tsung-Han Tsai
  • Patent number: 10587041
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 10, 2020
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 10587037
    Abstract: An electronic package structure is provided, including a substrate, a package encapsulant disposed on the substrate, and an antenna structure corresponding to a disposing area of the package encapsulant and having a first extension layer, a second extension layer disposed on the substrate, and a connection portion disposed between and electrically connected to the first extension layer and the second extension layer. Through the formation of the antenna structure on the disposing area of the package encapsulant, the substrate is not required to be widen, and, as such, the electronic package structure meets the miniaturization requirement.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 10, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Heng-Cheng Chu, Chien-Cheng Lin, Tsung-Hsien Tsai, Chao-Ya Yang, Yude Chu
  • Publication number: 20200067158
    Abstract: A novel miniaturized horizontal split-wave orthomode transducer includes a common channel portion, a first polarized channel portion and a second polarized channel portion, and the centers of the openings of the first polarized channel and the second polarized channel are coaxially and respectively arranged on two opposite sides of the common channel portion to save the bend and extended structure at the rear end of the horizontal split-wave orthomode transducer and also save the occupied space since there is no need to guide signals in one of the polarization directions to the rear and return the signals, so as to further achieve the effects of improving the flexibility of installing the transducer, providing a good isolation between electromagnetic signals in different polarization directions and preventing the interference occurred between the electromagnetic signals.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Applicant: UNIVERSAL MICROWAVE TECHNOLOGY, INC.
    Inventors: YU-CHENG CHEN, XUAN-WEI ZHANG, JEN-TI PENG, HSIU-YUN LIU, WEI-CHEN CHIEN, HSUEH-HAN CHEN, TSUNG-HSIEN TSAI
  • Publication number: 20200058535
    Abstract: A wafer carrier handling apparatus includes a housing, a platform, a moving mechanism and a door storage device. The platform is configured to hold a wafer carrier. The moving mechanism is connected to the housing and configured to move the platform with respect to the housing. The door storage device is disposed above the housing. The door storage device has a first door storage zone. The first door storage zone is configured to allow a door of the wafer carrier to be held thereon.
    Type: Application
    Filed: April 26, 2019
    Publication date: February 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Sheng KUO, Chih-Hung HUANG, Ming-Hsien TSAI, Yang-Ann CHU, Hsuan LEE, Jiun-Rong PAI