Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

Abstract: A magnetron mechanism of an unpowered treadmill contains: a driving body, a one-way transmission element, and a magnetron mechanism. The driving body includes a frame, a connection fence, a front wheel assembly, and a connection shaft. The one-way transmission element is mounted on the connection fence of the frame. The magnetron mechanism is fixed on the connection fence and includes a rotary shaft, a drive wheel, a driven wheel, a belt, a flywheel, a resistance element, and an adjustment unit. The resistance element has a pair of fixing sheets and multiple magnetic parts. Each of the multiple magnetic parts has a rotatable connection portion. The adjustment unit has a steel cable, an end of which is connected with the resistance element so that the steel cable pulls the resistance element to swing along the rotatable connection portion.

Abstract: A zeroing structure applicable to an adjustable diplexer includes a substrate, holder, motor, lead screw, displacement plate, stop element and interference element. The holder is disposed on the substrate. The motor is disposed on the holder. The lead screw is rotatably disposed on the holder and connected to the motor, and thus rotation of the lead screw is driven by the motor. The displacement plate is movably disposed on the substrate and helically connected to the lead screw so as to undergo linear motion between a first position and a second position relative to the substrate when guided and driven by the motor. The stop element is disposed on the lead screw. The interference element is disposed on the displacement plate and at the position that allows the interference element to come into contact with the stop element when the displacement plate is at the first position.

Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.

Abstract: A statistical performance evaluation method for different grouping sets includes setting a plurality of first grouping ranges of a first grouping set corresponding to a sample space, setting a plurality of second grouping ranges of a second grouping set corresponding to the sample space, generating a plurality of first probability values and a plurality of first standard deviations corresponding to the plurality of first grouping ranges at each sampling time according to the sample space, generating a plurality of second probability values and a plurality of second standard deviations corresponding to the plurality of second grouping ranges at the each sampling time according to the sample space, and generating a plurality of statistical indicators corresponding to the first grouping set and the second grouping set and outputting a statistical performance ranking result of the first grouping set and the second grouping set accordingly.

Abstract: A novel miniaturized horizontal split-wave orthomode transducer includes a common channel portion, a first polarized channel portion and a second polarized channel portion, and the centers of the openings of the first polarized channel and the second polarized channel are coaxially and respectively arranged on two opposite sides of the common channel portion to save the bend and extended structure at the rear end of the horizontal split-wave orthomode transducer and also save the occupied space since there is no need to guide signals in one of the polarization directions to the rear and return the signals, so as to further achieve the effects of improving the flexibility of installing the transducer, providing a good isolation between electromagnetic signals in different polarization directions and preventing the interference occurred between the electromagnetic signals.

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A system of training behavior labeling model is provided. Specifically, a processing unit inputs each data of a training data set into a plurality of learning modules to establish a plurality of labeling models. The processing unit obtains a plurality of second labeling information corresponding to each data of a verification data set and generates a behavior labeling result according to the second labeling information corresponding to each data of the verification data set. The processing unit obtains a labeling change value according to the behavior labeling result and first labeling information corresponding to each data of the verification data set. The processing unit, if determining that the labeling change value is greater than a change threshold, updates the first labeling information according to the behavior labeling results, exchanges the training data set and the verification data set and reestablishes the labeling models.

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

Abstract: A method for detecting abnormality adapted to detect abnormal operations of an operating system is provided. The method includes: calculating a safe range of usage of the operating system during one or more time periods according to a historical data stream; calculating abnormal ratios corresponding to the one or more time periods according to a current data stream and the safe range of usage; selecting one or more abnormal time periods from the one or more time periods according to a threshold and the abnormal ratios; calculating an abnormal indicator for each of the one or more abnormal time periods according to the historical data stream and the current data stream; and ranking the one or more abnormal time periods according to the abnormal indicator(s).

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.

Abstract: An electronic package structure is provided, including a substrate, a package encapsulant disposed on the substrate, and an antenna structure corresponding to a disposing area of the package encapsulant and having a first extension layer, a second extension layer disposed on the substrate, and a connection portion disposed between and electrically connected to the first extension layer and the second extension layer. Through the formation of the antenna structure on the disposing area of the package encapsulant, the substrate is not required to be widen, and, as such, the electronic package structure meets the miniaturization requirement.

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

Abstract: A novel miniaturized horizontal split-wave orthomode transducer includes a common channel portion, a first polarized channel portion and a second polarized channel portion, and the centers of the openings of the first polarized channel and the second polarized channel are coaxially and respectively arranged on two opposite sides of the common channel portion to save the bend and extended structure at the rear end of the horizontal split-wave orthomode transducer and also save the occupied space since there is no need to guide signals in one of the polarization directions to the rear and return the signals, so as to further achieve the effects of improving the flexibility of installing the transducer, providing a good isolation between electromagnetic signals in different polarization directions and preventing the interference occurred between the electromagnetic signals.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.