Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.

Abstract: A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.

Abstract: An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.

Abstract: A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

Abstract: A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.

Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

Abstract: A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

Abstract: An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.

Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

Abstract: A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

Abstract: A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

Abstract: A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer.

Abstract: A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.

Abstract: A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang.

Abstract: A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon layer, an oxide layer and a nitride layer, wherein the nitride layer has been pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without damaging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the sidewalls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio (D/S>10) and low bias power to form a thin layer, with no overhang, that is capable of protecting the nitride layer during subsequent deposition and sputtering steps.