Patents by Inventor Tsung-Te Chou

Tsung-Te Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10699977
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Publication number: 20190333829
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che CHEN, Tsung-Te CHOU, Chen-Hua LIN, Huang-Wen TSENG, Chwen-Ming LIU
  • Patent number: 10347548
    Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Publication number: 20180294392
    Abstract: A composite conducive to heat dissipation of an LED-mounted substrate includes a ceramic layer being of a thermal conductivity of 20˜24 W/mK; a metal layer being of a thermal conductivity of 100˜200 W/mK; and a graphite layer being of an in-plane thermal conductivity of 950 W/mK and a through-plane thermal conductivity of 3 W/mK, wherein the metal layer is disposed between the ceramic layer and the graphite layer. The composite has one side displaying satisfactory insulation characteristics and the other side displaying satisfactory heat transfer characteristics. The composite incurs low material costs and requires a simple manufacturing process.
    Type: Application
    Filed: April 6, 2017
    Publication date: October 11, 2018
    Inventors: BIING-JYH WENG, SHAO-YU WANG, HSIN-PING CHANG, WEI-HSING TUAN, TSUNG-TE CHOU
  • Publication number: 20180156865
    Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 7, 2018
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 9786628
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20170069593
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: Bruce C.S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9502396
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9443796
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Xin-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20160163684
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Bruce C.S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20140264948
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Application
    Filed: May 15, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C.S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Xin-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen