Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.

Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.

Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.

Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.

Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.

Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.

Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).

Abstract: A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion portion and transistors of the pixel are provided at a predetermined potential.

Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).

Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).

Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (OV), and a negative power source potential (for example ?1V).

Abstract: An image sensor includes a solid-state image pickup device, an optical system, and a flash. The solid-state image pickup device has an electronic shutter function of outputting accumulated signal charges at a timing corresponding to a shutter speed. The optical system collects incident light to an image pickup area of the solid-state image pickup device. The flash irradiates light to an object to be photographed by the solid-state image pickup device. The solid-state image pickup device includes a pulse generator circuit for generating one or more of an electronic shutter pulse for controlling an accumulation time of signal charges by using the electronic shutter function, an optical system movement pulse for controlling movement of the optical system, and a flash pulse for controlling an emission timing of the flash.

Abstract: A solid-state imaging device includes: an imaging unit taking a subject image focused by an imaging optical system; a digital signal processing unit generating image data of the subject image taken by the imaging unit and luminance data thereof; an input/output unit inputting and outputting data; a focus evaluation value generating unit generating a focus evaluation value of the subject image based on the luminance data outputted from the digital signal processing unit and outputting the focus evaluation value from the input/output unit; and an imaging drive unit starting an imaging operation by the imaging unit when an imaging instruction signal is inputted from the input/output unit, and outputting an imaging-end timing signal from the input/output unit when the imaging operation is completed.

Abstract: A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).

Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).

Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).

Abstract: From a pixel array where imaging pixels are arranged, pixel signals of respective columns on a selected row are read in parallel in a horizontal blanking period of a horizontal period. The pixel signals of the respective columns are output to horizontal signal lines in an effective period of the horizontal period via charge integrating amps provided respectively for the columns, i.e., provided respectively for vertical signal lines, and are thereby transferred horizontally. In the charge integrating amps, it is possible to enter a standby state while holding the pixel signals by a holding voltage. Furthermore, in the charge integrating amps, a reference potential for precharging feedback capacitors for amps at the time of a reading operation is automatically controlled based on a black level. Furthermore, pixel signals from the respective charge integrating amps are horizontally transferred in parallel using a plurality of horizontal signal lines.

Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion portion and transistors of the pixel are provided at a predetermined potential.