Abstract: A semiconductor manufacturing apparatus includes: a gas introduction pipe connected to a processing container of the semiconductor manufacturing apparatus in order to introduce a gas into the processing container; and a temperature sensor provided in the gas introduction pipe in order to measure a temperature of a gas in the gas introduction pipe.

Abstract: A pipette includes a capillary, a pressure chamber, a drive unit, and a control unit. The capillary has a first end and a second end that are two ends in a length direction and that are open. The pressure chamber communicates with an inside of the capillary via the second end. The drive unit changes a volume of the pressure chamber. The control unit controls the drive unit. The control unit outputs a vibrational movement signal that drives the drive unit so that a liquid moves from a mid-position in the capillary to a finish position that is located closer to the second end than the mid-position. The vibrational movement signal has a waveform that drives the drive unit so that the volume of the pressure chamber alternately increases and decreases repeatedly.

Abstract: In a pipette tip that is open at opposite distal and proximal ends, a glass tube has a first end adjacent to the distal end, a second end adjacent to the proximal end, and a first through hole extending therethrough from the first end to the second end. A connecting member has a second through hole with the glass tube inserted therein. The glass tube is at least partially inserted in the second through hole on one side adjacent to the second end, and is entirely located outside the second through hole on the other side adjacent to the first end. A diameter of an end portion of the connecting member opposite the distal end is greater than a diameter of the distal end of the pipette tip, and the connecting member is made of resin.

Abstract: A sensor substrate includes an insulating substrate including a plurality of inorganic particles formed of an insulator in contact with each other and glass, and a wiring conductor disposed on the insulating substrate. The plurality of inorganic particles and the glass are in contact with the wiring conductor, and the glass is disposed at a position between the plurality of inorganic particles and the wiring conductor, and a contact portion between the plurality of inorganic particles and the wiring conductor is larger than a contact portion between the glass and the wiring conductor in a longitudinal sectional view.

Abstract: A sensor substrate includes an insulating substrate including a plurality of inorganic particles formed of an insulator in contact with each other and glass, and a wiring conductor disposed on the insulating substrate. The plurality of inorganic particles and the glass are in contact with the wiring conductor, and the glass is disposed at a position between the plurality of inorganic particles and the wiring conductor, and a contact portion between the plurality of inorganic particles and the wiring conductor is larger than a contact portion between the glass and the wiring conductor in a longitudinal sectional view.

Abstract: A radio apparatus includes a first receiver that is a processing unit for amplifying and frequency converting a radio signal received via an antenna, thereby outputting an IF signal; a detector unit for detecting a preamble signal from the IF signal; a second receiver for amplifying and quadrature demodulating the radio signal, thereby generating an I-signal and a Q-signal; a demodulator unit for demodulating the I-signal and Q-signal to generate a data signal; and a control unit for halting the operation of the first receiver and further activating the second receiver when the detector unit detects the preamble signal and for activating the first receiver and halting the operation of the second receiver when the demodulator unit completes the demodulation of the I-signal and Q-signal.

Abstract: A radio apparatus includes an antenna; an amplifier that amplifies a radio signal, received via the antenna; a first mixer that frequency converts the amplified radio signal to generate a first analog signal; a first A/D converter that converts the first analog signal to generate a first digital signal; a second mixer that frequency converts the amplified signal to generate a second analog signal; a second A/D converter means that converts the second analog signal to generate a second digital signal; a demodulator means that demodulates the first and second digital signals to generate a demodulated signal; a detector that detects a preamble from the first digital signal; and a control means that halts the second mixer and second A/D converter during the wait for the radio signal and that activates the second mixer and second A/D converter when the detector detects the preamble.

Abstract: A radio apparatus includes a first receiver that is a processing unit for amplifying and frequency converting a radio signal received via an antenna, thereby outputting an IF signal; a detector unit for detecting a preamble signal from the IF signal; a second receiver for amplifying and quadrature demodulating the radio signal, thereby generating an I-signal and a Q-signal; a demodulator unit for demodulating the I-signal and Q-signal to generate a data signal; and a control unit for halting the operation of the first receiver and further activating the second receiver when the detector unit detects the preamble signal and for activating the first receiver and halting the operation of the second receiver when the demodulator unit completes the demodulation of the I-signal and Q-signal.

Abstract: A radio apparatus includes an antenna; an amplifier that amplifies a radio signal, received via the antenna; a first mixer that frequency converts the amplified radio signal to generate a first analog signal; a first A/D converter that converts the first analog signal to generate a first digital signal; a second mixer that frequency converts the amplified signal to generate a second analog signal; a second A/D converter means that converts the second analog signal to generate a second digital signal; a demodulator means that demodulates the first and second digital signals to generate a demodulated signal; a detector that detects a preamble from the first digital signal; and a control means that halts the second mixer and second A/D converter during the wait for the radio signal and that activates the second mixer and second A/D converter when the detector detects the preamble.

Abstract: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.

Abstract: In a read circuit, a write circuit writes a data to be stored and/or a test data to the memory cell. A control circuit controls the write circuit to write the test data to the memory cell in a first phase, and to write the test data which is same as the first phase to the memory cell in a second phase. An integrator integrates voltages at one terminal of the memory cell during the first phase to obtain a first integrated voltage, and integrates voltages at one terminal of the memory cell during the second phase to obtain a second integrated voltage. A buffer stores the first integrated voltage. A comparator compares the first integrated voltage from the buffer with the second integrated voltage from the integrator to obtain the data.

Abstract: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.

Abstract: A magnetic memory device including a plurality of word lines, a plurality of bit lines which intersect the word lines and are put into groups, a plurality of memory cells which are arranged at intersections between the bit lines and the word lines, each memory cell including a magnetic element and a transistor which are connected in series, a first decoder which sequentially selects the word lines, a second decoder which sequentially drives the bit lines of each group, a weighting adder which performs weighting addition of currents flowing on bit lines in a selected group to generate an added current signal, a current/voltage converter which converts the added current signal into a voltage signal, and an analog-to-digital converter which digitizes the voltage signal.

Abstract: A magnetic memory device includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read current source which supplies a read current to the MRAM cells in a read mode, a sense amplifier which detects terminal voltages of the MRAM cells generated by the read current to generate a detection output signal, a latch circuit which latches the detection output signal to output read data, and a data write circuit which supplies a write current to the MRAM cells depending on write data in a write mode to perform writing and which supplies the write current to the MRAM cells depending on the read data in the read mode to perform rewriting.

Abstract: In a read circuit, a write circuit writes a data to be stored and/or a test data to the memory cell. A control circuit controls the write circuit to write the test data to the memory cell in a first phase, and to write the test data which is same as the first phase to the memory cell in a second phase. An integrator integrates voltages at one terminal of the memory cell during the first phase to obtain a first integrated voltage, and integrates voltages at one terminal of the memory cell during the second phase to obtain a second integrated voltage. A buffer stores the first integrated voltage. A comparator compares the first integrated voltage from the buffer with the second integrated voltage from the integrator to obtain the data.

Abstract: A magnetic memory device includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read current source which supplies a read current to the MRAM cells in a read mode, a sense amplifier which detects terminal voltages of the MRAM cells generated by the read current to generate a detection output signal, a latch circuit which latches the detection output signal to output read data, and a data write circuit which supplies a write current to the MRAM cells depending on write data in a write mode to perform writing and which supplies the write current to the MRAM cells depending on the read data in the read mode to perform rewriting.

Abstract: A magnetic memory device including a plurality of word lines, a plurality of bit lines which intersect the word lines and are put into groups, a plurality of memory cells which are arranged at intersections between the bit lines and the word lines, each memory cell including a magnetic element and a transistor which are connected in series, a first decoder which sequentially selects the word lines, a second decoder which sequentially drives the bit lines of each group, a weighting adder which performs weighting addition of currents flowing on bit lines in a selected group to generate an added current signal, a current/voltage converter which converts the added current signal into a voltage signal, and an analog-to-digital converter which digitizes the voltage signal.

Abstract: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.

Abstract: A transfer control device is arranged between a bus and a bus interface. The transfer control device includes a bus connecting unit that is connected to plural signal lines of the bus, an interface connecting unit that is connected to plural signal lines of the bus interface, and a connection control unit that connects, when a defective signal line exists in the plural signal lines of the bus, a signal line corresponding to the defective signal line out of the plural signal lines of the bus interface and a signal line other than the defective signal line out of the plural signal lines of the bus.

Abstract: A method, apparatus and system for controlling the reading and writing of flash memories including a write control section, a plurality of read enable control signal lines and a read control section. The write control section configured to supply a write command, a write head address and first data to each of the flash memories through a bus at a predetermined timing to cause one of the flash memories to perform a write mode for writing sequentially first data from a memory address of a corresponding one of the flash memories which is accessed by the write head address in response to the write command, the write head address and first data being supplied at a predetermined timing without fetching any external signal within a first time period. The plurality of read enable control signal lines connected to the plurality of flash memories, respectively, to assign individually a plurality of read enable control signals to the flash memories via the signal lines.