Patents by Inventor Tsuyoshi Kachi

Tsuyoshi Kachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194548
    Abstract: A semiconductor substrate is easily warped by the shrink of the insulating film formed within the deep trench according to the thermal processing in the super junction structure. In order to solve the above problem, in a semiconductor device, an element region and a terminal region are defined on one main surface of the semiconductor substrate. The terminal region is arranged to surround the element region. In the terminal region, a plurality of buried insulators are formed from the main surface of the semiconductor substrate in a way of penetrating an n-type diffusion layer and an n-type column layer and arriving at an n-type epitaxial layer. The buried insulator is formed within a deep trench. The plural buried insulators are arranged in island shapes mutually at a distance from each other.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventors: Yoshinori YOSHIDA, Tsuyoshi KACHI
  • Patent number: 10615251
    Abstract: A semiconductor substrate is easily warped by the shrink of the insulating film formed within the deep trench according to the thermal processing in the super junction structure. In order to solve the above problem, in a semiconductor device, an element region and a terminal region are defined on one main surface of the semiconductor substrate. The terminal region is arranged to surround the element region. In the terminal region, a plurality of buried insulators are formed from the main surface of the semiconductor substrate in a way of penetrating an n-type diffusion layer and an n-type column layer and arriving at an n-type epitaxial layer. The buried insulator is formed within a deep trench. The plural buried insulators are arranged in island shapes mutually at a distance from each other.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Yoshida, Tsuyoshi Kachi
  • Patent number: 10381435
    Abstract: A deep trench which reaches a predetermined depth from one principal surface is formed in an element region of a semiconductor substrate. A TEOS oxide film and a polycrystalline silicon film are formed so as to fill the deep trench. In formation of a MOSFET and in formation of a protective insulating film on/over a surface of an element region by thermal oxidation, a silicon thermal oxide film grows, the TEOS oxide film contracts and the polycrystalline silicon film expands when oxidized and turning into a silicon oxide film, and thereby an embedded insulator is formed in the deep trench.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Senichirou Nagase, Tsuyoshi Kachi, Yoshinori Hoshino
  • Publication number: 20190198660
    Abstract: There is provided a semiconductor device and its manufacturing method capable of avoiding generation of a through-current flowing between the drain and source and suppressing the potential fluctuation with time in the field plate electrode. A drain region is arranged on a first surface of a semiconductor substrate, a source region is arranged on a second surface thereof, and a drift region is arranged between the drain region and the source region. The semiconductor substrate has a trench extending from the second surface into the drift region. The field plate electrode is arranged within the trench to be electrically insulated from the drain region and insulated from the drift region oppositely. The Zener diode is electrically coupled between the source region and the field plate electrode. The Zener diode is coupled in a forward direction from the source region to the field plate electrode.
    Type: Application
    Filed: November 8, 2018
    Publication date: June 27, 2019
    Inventor: Tsuyoshi KACHI
  • Publication number: 20190131448
    Abstract: Provided are a semiconductor device including a desired snubber part in accordance with use of the semiconductor device and a method of manufacturing the semiconductor device. A snubber region having a snubber part is defined in a gate pad region defined on a side close to a first main surface of a semiconductor substrate. A p-type diffusion layer and an n-type column layer contacted to each other are formed in the snubber region. The p-type diffusion layer and the n-type column layer are formed as a parasitic capacitance of the snubber part while the n-type column layer is electrically coupled to a drain. The p-type diffusion layer, which extends in a Y-axis direction, is a resistance of the snubber part and electrically coupled to a source.
    Type: Application
    Filed: August 29, 2018
    Publication date: May 2, 2019
    Inventors: Yoshinori YOSHIDA, Tsuyoshi KACHI
  • Publication number: 20190043943
    Abstract: A semiconductor substrate is easily warped by the shrink of the insulating film formed within the deep trench according to the thermal processing in the super junction structure. In order to solve the above problem, in a semiconductor device, an element region and a terminal region are defined on one main surface of the semiconductor substrate. The terminal region is arranged to surround the element region. In the terminal region, a plurality of buried insulators are formed from the main surface of the semiconductor substrate in a way of penetrating an n-type diffusion layer and an n-type column layer and arriving at an n-type epitaxial layer. The buried insulator is formed within a deep trench. The plural buried insulators are arranged in island shapes mutually at a distance from each other.
    Type: Application
    Filed: June 27, 2018
    Publication date: February 7, 2019
    Inventors: Yoshinori YOSHIDA, Tsuyoshi KACHI
  • Patent number: 10164087
    Abstract: To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Senichirou Nagase, Tsuyoshi Kachi, Yoshinori Hoshino
  • Publication number: 20180358434
    Abstract: A deep trench which reaches a predetermined depth from one principal surface is formed in an element region of a semiconductor substrate. A TEOS oxide film and a polycrystalline silicon film are formed so as to fill the deep trench. In formation of a MOSFET and in formation of a protective insulating film on/over a surface of an element region by thermal oxidation, a silicon thermal oxide film grows, the TEOS oxide film contracts and the polycrystalline silicon film expands when oxidized and turning into a silicon oxide film, and thereby an embedded insulator is formed in the deep trench.
    Type: Application
    Filed: April 11, 2018
    Publication date: December 13, 2018
    Inventors: Senichirou NAGASE, Tsuyoshi KACHI, Yoshinori HOSHINO
  • Publication number: 20180019160
    Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent the breakage of an element and in which the control of impurity amounts is less susceptible to variations in manufacturing processes. A semiconductor substrate has a front surface and includes hole portions extending from the front surface to an inside of the substrate. N-type regions are formed in the semiconductor substrate. At wall surfaces of the hole portions, p-type regions are formed to configure p-n junction with the n-type regions. Each of the p-type regions includes a low-concentration region and a high-concentration region formed at the wall surface of each hole portion. A width of the high-concentration region along the wall surface of the hole portion becomes smaller from the front surface toward a deeper position.
    Type: Application
    Filed: May 11, 2017
    Publication date: January 18, 2018
    Inventors: Tsuyoshi KACHI, Yoshinori HOSHINO, Senichirou NAGASE
  • Patent number: 9780187
    Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Ikegami, Tsuyoshi Kachi
  • Publication number: 20170229572
    Abstract: To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region.
    Type: Application
    Filed: February 9, 2017
    Publication date: August 10, 2017
    Inventors: Senichirou NAGASE, Tsuyoshi KACHI, Yoshinori HOSHINO
  • Publication number: 20160308022
    Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 20, 2016
    Inventors: Yuta IKEGAMI, Tsuyoshi KACHI
  • Patent number: 9406787
    Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 2, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Ikegami, Tsuyoshi Kachi
  • Patent number: 9397156
    Abstract: To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 19, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Tsuyoshi Kachi
  • Patent number: 9397160
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: July 19, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Yoshida, Hirokazu Kato, Tsuyoshi Kachi, Keisuke Furuya
  • Publication number: 20160079352
    Abstract: To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Inventor: Tsuyoshi Kachi
  • Publication number: 20160043206
    Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.
    Type: Application
    Filed: July 22, 2015
    Publication date: February 11, 2016
    Inventors: Yuta IKEGAMI, Tsuyoshi KACHI
  • Patent number: 9231082
    Abstract: A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Koichiro Sakanishi, Tsuyoshi Kachi, Koji Fujishima
  • Publication number: 20150380487
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Yoshinori Yoshida, Hirokazi Kato, Tsuyoshi Kachi, Keisuke Furuya
  • Patent number: 9209249
    Abstract: To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: December 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Tsuyoshi Kachi