Abstract: The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers (12a˜120 are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers (12a˜120 respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [?m], and the number of the plurality of units is num, following relationships are satisfied. N?(M×BV)?, M=104 to 105, ?=0.55 to 1.95, SandL×num×Ecri?2×?×BV, Ecri=2.0 to 3.0×105 [V/cm], ?=100 to 101. Widths of the P-type ring layers (12a˜12f) of the plurality of units linearly decrease toward an outside of the termination region.

Abstract: An electric field buffer layer (13) is formed so as to surround an active region (12) from an outer peripheral portion of the active region (12) toward an outer peripheral portion of a semiconductor substrate (11). The electric field buffer layer (13) includes a plurality of P-type impurity layers (21 to 25). Each of the P-type impurity layers (21 to 25) includes P-type implantation layers (21a to 25a) and P-type diffusion layers (21b to 25b) that are formed so as to respectively surround the P-type implantation layers (21a to 25a) and contain P-type impurities at a concentration lower than that of the P-type implantation layers (21a to 25a). A first P-type implantation layer (21a) is formed to be in contact with or to partially overlap the active region (12). Each of the P-type diffusion layers (21b to 25b) is formed to have an expansion to a degree to which the first P-type diffusion layer (21b) is in contact with or overlaps a second P-type diffusion layer (22b).

Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.

Abstract: A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a port ion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.

Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract: A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.

Abstract: A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a portion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.

Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11?) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13?) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple.

Abstract: A power amplifier device that satisfies both delivering a high output and reducing the chip area occupied by the power amplifier device. Over a substrate, are primary inductors arranged in a generally circular geometry, a ground pattern, transistor pairs, and a secondary inductor. The ground pattern extends from a portion of a region inside the circular primary inductor into regions outside the primary inductor, and grounded at a plurality of points in the regions outside the primary inductor. The primary inductors are coupled to the ground pattern through transistors.

Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.

Abstract: A power amplifier device that satisfies both delivering a high output and reducing the chip area occupied by the power amplifier device. Over a substrate, are primary inductors arranged in a generally circular geometry, a ground pattern, transistor pairs, and a secondary inductor. The ground pattern extends from a portion of a region inside the circular primary inductor into regions outside the primary inductor, and grounded at a plurality of points in the regions outside the primary inductor. The primary inductors are coupled to the ground pattern through transistors.

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.