Abstract: A computer-readable storage medium storing program instructions to perform a method of classification of short time series in order to detect a neurodegenerative disorder. The method includes receiving a plurality of sensor data collected from subjects with and without the neurodegenerative disorder over a period of a few seconds as the short time series, generating phase-space vectors from the plurality of sensor data in which each vector is a state of a dynamical system in space and time, transforming the phase-space vectors into a grayscale image representing recurrences of a state-space vector in the same area of the phase space, extracting temporal texture features of the grayscale image to obtain a multi-dimensional time series; inputting the multidimensional time series, without the grayscale image, to the Long Short Term Memory (LSTM) network, and classifying, by the LSTM network, the plurality of the sensor data as the neurodegenerative disorder or not.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.

Abstract: An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering the floating gate has a second thickness which is greater than the first thickness of the floating gate. The method further includes polishing the insulator until the second thickness is substantially equal to the first thickness. Polishing results in a planar floating gate and insulator layer. The method further includes sequentially depositing a dielectric layer and a control gate layer on the planar floating gate and insulator layer and then etching these layers to complete the stacked gate structure of the memory cell.

Abstract: A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer. Periphery stacks have hate oxide layers of different thicknesses.

Abstract: A multilayer electrically conductive stack is formed in a semiconductor device prior to one step of photolithography. In this multilayer electrically conductive stack, alternate layers of the stack contain materials that differ in their refractive indices. In one instance, the electrically conductive stack can serve as an anti-reflective coating in the photolithographical processing. As the electrically conductive stack has chemical and electrical properties similar to those of an underlying device structures, removal of the multilayer stack after the photolithographical step is not required. In one instance, the electrically conductive stack can be used to form a gate structure or an interconnect structure. In an embodiment of the invention, alternate layers consist of Si1−xGex and Si, respectively.

Abstract: A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.

Abstract: A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.

Abstract: An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

Abstract: An improved flash memory device, which has shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.

Abstract: A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device.