Abstract: The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.

Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order.

Abstract: An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

Abstract: A method and apparatus are provided to enable snoop forwarding to occur together with memory protection. A data processing apparatus in, for instance, the form of a home node forwards a snoop forwarding request on behalf of a requester to a target, the snoop forwarding request being capable of indicating one or more access permissions of the target in relation to the data. A further data processing apparatus in the form of, for instance, a receiver node may receive the snoop forwarding request and based on its own permissions that are provided in the snoop forwarding request, together with the state of the data, either provide a response back to the requester or the home node. In a still further data processing apparatus in the form of, for instance, a Memory Protection Unit (MPU), a regular snoop forwarding request made to a target in relation to data can be forwarded to the target or demoted to a non-forwarding snoop request based on the permissions of the target in relation to the data at the MPU.

Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.

Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

Abstract: A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.

Abstract: A method and apparatus are provided to enable snoop forwarding to occur together with memory protection. A data processing apparatus in, for instance, the form of a home node forwards a snoop forwarding request on behalf of a requester to a target, the snoop forwarding request being capable of indicating one or more access permissions of the target in relation to the data. A further data processing apparatus in the form of, for instance, a receiver node may receive the snoop forwarding request and based on its own permissions that are provided in the snoop forwarding request, together with the state of the data, either provide a response back to the requester or the home node. In a still further data processing apparatus in the form of, for instance, a Memory Protection Unit (MPU), a regular snoop forwarding request made to a target in relation to data can be forwarded to the target or demoted to a non-forwarding snoop request based on the permissions of the target in relation to the data at the MPU.

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

Abstract: Apparatus and a corresponding method of operating the apparatus, in a coherent interconnect system comprising a requesting master device and a data-storing slave device, are provided. The apparatus maintains records of coherency protocol transactions received from the requesting master device whilst completion of the coherency protocol transactions are pending and is responsive to reception of a read transaction from the requesting master device for a data item stored in the data-storing slave device to issue a direct memory transfer request to the data-storing slave device. A read acknowledgement trigger is added to the direct memory transfer request and in response to reception of a read acknowledgement signal from the data-storing slave device a record created by reception of the read transaction is updated corresponding to completion of the direct memory transfer request.

Abstract: A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: In a data processing network comprising a Request, Home and Slave Nodes coupled via a coherent interconnect, a Home Node performs a read transaction in response to a read request from a Request Node. In a first embodiment, the transaction is terminated in the Home Node upon receipt of a read receipt from a Slave Node, acknowledging a read request from the Home Node. In a second embodiment, the Home Node sends a message to the Request Node indicating that a read transaction has been ordered in the Home Node and further indicating that data for the read transaction is provided in a separate data response. The transaction is terminated in the Home Node upon receipt of an acknowledge from the Request Node of this message. In this manner, the transaction is terminated in the Home Node without waiting for acknowledgement from the Request Node of completion of the transaction.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.