Abstract: An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.

Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

Abstract: Various methods and apparatuses are described in which a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.

Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.

Abstract: An metal programmable integrated circuit apparatus and method of manufacture and design using elevated metal layers for design-specific customization. The lower metal layer are used to form core cells and to provide power and clocking signals to the core cells. These core cell are customizable by the designer using only the upper metal layers. This new architecture allows faster turn-around time and fewer masks while keeping the time-to-market advantages of gate array structures.

Abstract: A user customizable integrated circuit architecture having separate regions for different types of core cells. In an embodiment of the present invention, all asynchronous core cells are placed in a first region and all synchronous core cells are placed in a second region thus allowing clock circuitry to be shared and clock traces to be efficiently routed. Clock buffers may also be placed in the second region. In a second embodiment, high-drive buffers are placed in the second region to enable efficient routing of high-drive power traces to the synchronous cells. Each region also may include metal programmable core cells that may be customized by the user for each design.

Abstract: A layout architecture for routing local and global interconnections for a gate array integrated circuit wherein basic cells are arranged as an array with columns and rows. Local interconnection and global interconnections are routed on the first metal layer in a direction parallel to the rows (horizontal). Power supply signals and global interconnection are routed in the second metal layer in a direction parallel to the rows (horizontal). Global interconnections are routed on the third metal layer in a direction parallel to the columns (vertical).

Abstract: A CMOS cell architecture and routing technique is optimized for three or more interconnect layer cell based integrated circuits such as gate arrays. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend transverse to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire trace impedances, and reduced noise.

Abstract: A gate array basic cell and circuit layout architecture for efficiently routing power supply traces. A basic cell has one or more transistors PMOS and one or more NMOS formed by diffusion regions and gate regions. A portion of the diffusion region extends outward to a point past the end of the gate region. Basic cells are arranged in rows with each basic cell having its p-type diffusion region extending in a direction opposite the n-type diffusion region. Basic cells are arranged in rows. Power supply traces are placed between rows, across the extended diffusion regions. Adjacent rows are shifted with respect to each other. A power supply trace is shared by adjacent rows of basic cells such that a connection can be made between the power supply trace and the extended diffusion regions without additional routing.

Abstract: A CMOS cell architecture and routing technique is optimized for three or more interconnect layer cell based integrated circuits such as gate arrays. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend transverse to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire trace impedances, and reduced noise.

Abstract: Methods and related structures for both operating and testing an integrated circuit constructed of combinations of customization logic and embedded cells. Functional modes include an operational mode and a test mode with two submodes. Test terminals of embedded cells, as well as test points in customization logic, are both accessed via a multiplexing scheme using test points of x-y (row and column) wiring traces of a grid-based "cross-check" test structure for both logic testing and embedded cell testing. Common conductors or traces can be used to operate the embedded cells and to control the made and test the embedded cells and customization logic. The x and y lines can be operated as signal lines, as probe lines, as sense lines and as control lines, as needed, using multiplexing according to the invention.

Abstract: A programmable interface apparatus between a first circuit and either a second operational circuit, or a primary pin, of an IC includes a latch for receiving a test signal. The latch is controlled using probe lines and sense lines from an internal test matrix. In one configuration, such an interface is programmably configured to couple either a primary input signal or a test signal to the operational circuitry. In another configuration, such an interface is programmably configured to couple either an operational circuit signal or a test signal to a primary output pin. In still another configuration, such an interface is programmably configured to couple either an operational circuit signal or a test signal to an operational circuit element. In one embodiment, the interface is formed with a pair of transmission gates, the latch and an invertor. An advantage of such structure is the minimal IC area required.

Abstract: A desired signal level is set at select storage elements of an integrated circuit without relying on signals applied to the primary input pins of the integrated circuit. Instead, a signal is applied through a test matrix to the input, output or internal line of a select storage element. With the drive of the applied signal being greater than the drive of the signals occurring at the select storage element of the integrated circuit, the applied signal level magnitude is forced upon the storage element. Once the drive of the applied signal is reduced relative to the drive of the storage element signals so as to be less than or equal to the drive of the storage element signals, the output level of the select storage element remains at the desired level. According to one embodiment, the power supply of the test electronics which generates the applied signal is of greater magnitude than the integrated circuit power supply at power up during the state-setting operation to achieve the greater relative drive.

Abstract: A new test structure is described which allows full testing of highly complex Integrated Circuits. The test structure consists of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of said probe and the sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe and sense lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines. Thus, by the excitation of an appropriate probe-line and the monitoring of an appropriate sense-line, the test signals present at any one of the test-points can be measured.

Abstract: An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults.

Abstract: Enhanced density of electrical and/or mechanical interconnections between adjacent wafers within integrated circuit assemblies and structural integrity of those interconnections under temperature cycling conditions, is attained by utilizing laser assisted chemical vapor deposition to fabricate precisely configured metal posts which serve as such interconnections.

Abstract: A new test structure is described which allows full testing of highly complex Integrated Circuits. The test structure consists of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of said probe and the sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe and sense lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines. Thus, by the excitation of an appropriate probe-line and the monitoring of an appropriate sense-line, the test signals present at any one of the test-points can be measured.

Abstract: A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), valid entries table (16) and an instruction table (18). Whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction, i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line.

Abstract: The invention is an all-soliton sampler for accessing very high speed circuits. A soliton is switched in two parallel branches, one including the device-under-test and the other including a programmable delay line implemented in soliton devices. The outputs of these two branches are used as controls to a soliton comparator which, in turn, controls a Josephson detector gate. This circuit permits a relatively slow rise time external trigger pulse to initiate an extremely narrow sampling pulse.

Abstract: A Josephson current regulator circuit is described for regulating the gate current to a Josephson load device. The regulator circuit is located between the source of the gate current and the Josephson load, and is comprised of Josephson devices having a critical current less than the critical current of the Josephson load device. Each of the Josephson regulator devices has at least two states dependent upon the magnitude of the gate current. A resistance is associated with each of the Josephson regulator devices so that, when the state of the Josephson regulator device is changed, resistance is either introduced or removed from the circuit connecting the source and the Josephson load. This adjusts the magnitude of the gate current and maintains within a specified range the ratio of the gate current to the critical current of the Josephson load device.