Abstract: A source driver including a digital-to-analog converter and an output buffer with an interpolation function is disclosed. A digital-to-analog converter converts a plurality of digital input voltages into a plurality of analog input voltages. The output buffer interpolates the analog input voltages. The output buffer outputs a first interpolated output voltage at a first time and a second interpolated output voltage at a second time respectively. A first interpolated voltage output curve of the first interpolated output voltage versus a digital input code and a second interpolated voltage output curve of the second interpolated output voltage versus the digital input code are both non-linear and opposite each other. The output buffer averages the first interpolated voltage output curve at the first time and the second interpolated voltage output curve at the second time to achieve a linear interpolated voltage characteristic.

Abstract: A source driver module, a display device and a method for driving a display panel are provided. The method for driving a display panel is applicable to the source driver module, which includes a source driver circuit, a first switch coupled between the source driver circuit and a first end of a first data line, and a second switch coupled between the source driver circuit and a second end of the first data line. The method for driving the display panel includes: when the display panel displays a first image, the source driver circuit outputs a first voltage signal to the first end of the first data line through the first switch, and when the display panel displays a second image after displaying the first image, the source driver circuit outputs a second voltage signal to the second end of the first data line through the second switch.

Abstract: A source driver including a digital-to-analog converter and an output buffer with an interpolation function is disclosed. A digital-to-analog converter converts a plurality of digital input voltages into a plurality of analog input voltages. The output buffer interpolates the analog input voltages. The output buffer outputs a first interpolated output voltage at a first time and a second interpolated output voltage at a second time respectively. A first interpolated voltage output curve of the first interpolated output voltage versus a digital input code and a second interpolated voltage output curve of the second interpolated output voltage versus the digital input code are both non-linear and opposite each other. The output buffer averages the first interpolated voltage output curve at the first time and the second interpolated voltage output curve at the second time to achieve a linear interpolated voltage characteristic.

Abstract: A display apparatus including a voltage buffer, a display panel and a pixel loading compensation circuit is disclosed. The voltage buffer is used to receive a ramp voltage and output an output current. The display panel includes pixel switches and pixel capacitors. The pixel switches are arranged in parallel and coupled to the voltage buffer. The pixel capacitors are coupled between the pixel switches and ground. The pixel loading compensation circuit includes compensation switches and compensation current sources. The compensation switches corresponding to the pixel switches are arranged in parallel and coupled to the voltage buffer. The compensation current sources are coupled between the compensation switches and ground. The operation of the compensation switches is opposite to the operation of the corresponding pixel switches.

Abstract: A display apparatus and a voltage calibration method are disclosed. The display apparatus includes a ramp voltage generator, a ramp counter and a timing controller. The ramp voltage generator is configured to generate a ramp voltage. The ramp counter is coupled to the ramp voltage generator and configured to start counting when the ramp voltage generator generates the ramp voltage. The timing controller is coupled to the ramp voltage generator and the ramp counter respectively. When the ramp voltage is increased to be equal to a reference voltage, the timing controller compares an instant count value of the ramp counter with a default value and selectively calibrates a rising slope of the ramp voltage generated by the ramp voltage generator according to a comparing result of the instant count value and the default value.

Abstract: A display panel driving device is configured to drive a display panel. The display panel driving device includes a driving unit, a digital circuit unit and a selecting unit. The driving unit includes a first channel and a second channel. The first channel includes a first amplifier, and the second channel comprises a second amplifier. The digital circuit unit is coupled to the driving unit, and configured to output a first signal and a second signal to the first channel and the second channel respectively. The selecting unit is coupled to the driving unit. When the first signal and the second signal are the same, the selecting unit optionally switches off the first amplifier or the second amplifier.

Abstract: The present invention provides a driving circuit, applied to an In-cell touch display panel. The In-cell touch display panel has a touch period and a data driving period. The touch period occurs between the data driving period corresponding to a first data line and another data driving period corresponding to a second data line. A common voltage (VCOM) voltage of the In-cell touch display panel has a first level and a second level. The driving circuit includes a determining module and a compensating module. The determining module determines whether a difference between the first level and the second level is larger than a preset value. The compensating module is coupled to the determining module. When the determining result is that the difference between the first level and the second level is larger than the preset value, the compensating module compensates the common voltage in the touch period, so that the first level and the second level are substantially equal.

Abstract: A display apparatus including a voltage buffer, a display panel and a pixel loading compensation circuit is disclosed. The voltage buffer is used to receive a ramp voltage and output an output current. The display panel includes pixel switches and pixel capacitors. The pixel switches are arranged in parallel and coupled to the voltage buffer. The pixel capacitors are coupled between the pixel switches and ground. The pixel loading compensation circuit includes compensation switches and compensation current sources. The compensation switches corresponding to the pixel switches are arranged in parallel and coupled to the voltage buffer. The compensation current sources are coupled between the compensation switches and ground. The operation of the compensation switches is opposite to the operation of the corresponding pixel switches.

Abstract: An amplifier circuit and a buffer amplifier are provided. The amplifier circuit includes an operational amplifier stage, an output stage, a first compensation capacitor, and a first decoupling circuit. The operational amplifier stage is coupled between a first input terminal, a second input terminal, a first control node, and a second control node. The first compensation capacitor is coupled between the output terminal and the first control node. The first decoupling circuit has a first switch, a first current source and a first ground terminal. The first switch is coupled to the first control node, and the first current source is connected between the first switch and the first ground terminal. The decoupling circuit is used for providing a discharging path for the first coupling current of the first compensation capacitor.

Abstract: A display apparatus and a voltage calibration method are disclosed. The display apparatus includes a ramp voltage generator, a ramp counter and a timing controller. The ramp voltage generator is configured to generate a ramp voltage. The ramp counter is coupled to the ramp voltage generator and configured to start counting when the ramp voltage generator generates the ramp voltage. The timing controller is coupled to the ramp voltage generator and the ramp counter respectively. When the ramp voltage is increased to be equal to a reference voltage, the timing controller compares an instant count value of the ramp counter with a default value and selectively calibrates a rising slope of the ramp voltage generated by the ramp voltage generator according to a comparing result of the instant count value and the default value.

Abstract: A source driver module, a display device and a method for driving a display panel are provided. The method for driving a display panel is applicable to the source driver module, which includes a source driver circuit, a first switch coupled between the source driver circuit and a first end of a first data line, and a second switch coupled between the source driver circuit and a second end of the first data line. The method for driving the display panel includes: when the display panel displays a first image, the source driver circuit outputs a first voltage signal to the first end of the first data line through the first switch, and when the display panel displays a second image after displaying the first image, the source driver circuit outputs a second voltage signal to the second end of the first data line through the second switch.

Abstract: A panel display position fine adjustment method is disclosed. The panel display position fine adjustment method includes steps of: (a) providing a fixed first synchronization timing signal; (b) generating a first control signal, a second control signal, and a third control signal according to the first synchronization timing signal, wherein the second control signal is turned on earlier than the first control signal and the third control signal is turned on later than the first control signal; (c) when the first display driver is controlled by the first control signal, the display area is not moved; (d) when the first display driver is controlled by the second control signal, the display area is moved in the first direction; and (e) when the first display driver is controlled by the third control signal, the display area is moved in the second direction opposite to the first direction.

Abstract: A source driver applied in a display includes a DAC and an output buffer. The DAC receives M-bits digital input voltage and converts it into 2M analog input voltages. M is a positive integer. The output buffer with interpolating function receives the 2M analog input voltages and increases them to K analog output voltages in a N-bits interpolating way. N is a positive integer and K=2M*2N=2(M+N). The output buffer includes a positive output buffer unit and a negative output buffer unit and generates a positive interpolating voltage and a negative interpolating voltage through them respectively to share the same source output channel of the source driver and achieve linear interpolation voltage characteristics through mutual compensation between the positive interpolating voltage and the negative interpolating voltage.

Abstract: A comparator control circuit includes a current source, a first input unit, a second input unit, switches, and a ground terminal. The current source generates an input current. The input current is divided into a first current flowing through the first input unit and a second current flowing through the second input unit. The first input unit receives a signal voltage. The second input unit receives a reference voltage. The first input unit and second input unit are coupled to the current source. The switches include a first switch and a second switch. The second switch has a control voltage. The ground terminal is coupled to the switches. When the first input unit is at high-level, the first switch is switched off and second switch is switched off by the control voltage to stop the second current flowing from the second input unit to the ground terminal.

Abstract: A display includes an array of pixel circuits and data drivers to drive the pixel circuits. The data drivers include a first data driver to receive pixel data according to a first clock frequency and to forward some of the pixel data to a second data driver according to a second clock frequency, the second clock frequency being different from the first clock frequency.

Abstract: In a display driver, image data are assembled with synchronization information to form a stream of digital data. The stream of digital data is transmitted from a timing controller to a data driver along with a timing signal having phase-delayed pulses obtained from an external clock received by the timing controller. In response to the timing signal, the data driver can extract a synchronizing signal from the synchronization information embedded in the stream of digital data, and use the synchronizing signal for generating an internal clock signal. Encoded image data in the stream of digital data then can be retrieved according to the internal clock signal.

Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A driving circuit of a flat panel display device includes a horizontal bus, a plurality of horizontal driver ICs, a vertical bus, and a plurality of vertical driver ICs. The horizontal driver IC is operative to decode N-types of vertical driving signals output from the horizontal bus, so as to transmit the N-type vertical driving signals to the corresponding vertical driver IC via a vertical signal line of the vertical bus.

Abstract: A chip-on-glass panel device includes a glass substrate having a pixel area, an integrated circuit area, and a fan out area, the fan out area located between the pixel area and the IC area, a plurality of integrated circuit devices arranged within the integrated area of the glass substrate, each of the plurality of integrated circuit devices have an active surface, a plurality of output pads, each arranged on the active surface, and a plurality of signal pads/gamma pads, each arranged on the active surface, and a plurality of signal wires/gamma wires, each having a curved shape geometry and disposed within the fan out area, for connecting the plurality of signal pads/gamma pads of adjacent ones of the plurality of integrated circuit devices through the fan out area.

Abstract: In a display driver, image data are assembled with synchronization information to form a stream of digital data. The stream of digital data is transmitted from a timing controller to a data driver along with a timing signal having phase-delayed pulses obtained from an external clock received by the timing controller. In response to the timing signal, the data driver can extract a synchronizing signal from the synchronization information embedded in the stream of digital data, and use the synchronizing signal for generating an internal clock signal. Encoded image data in the stream of digital data then can be retrieved according to the internal clock signal.