Patents by Inventor Tzu-Chiang Chen

Tzu-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10359544
    Abstract: A long-wave infrared anti-reflective laminate includes a silicon substrate and an anti-reflective composite layer. The anti-reflective composite layer is disposed on the silicon substrate and has at least one first anti-reflective membrane. The at least one first anti-reflective membrane includes a first silicon nitride layer and a first silicon dioxide layer. The first silicon nitride layer is disposed between the silicon substrate and the first silicon dioxide layer. The thickness ratio of the first silicon nitride layer to the first silicon dioxide layer ranges from 175 to 225. The anti-reflective composite layer can be applied on the optical instrument to raise the transmitting rate of the silicon substrate. The transmitting rate of the long-wave infrared anti-reflective laminate is over 90% within the wave band from 8 ?m to 12 ?m.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: July 23, 2019
    Inventor: Tzu-Chiang Chen
  • Patent number: 10355102
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 10297508
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Publication number: 20190148515
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: May 16, 2019
    Inventors: Chao-Ching CHENG, Yu-Lin YANG, Wei-Sheng YUN, Chen-Feng HSU, Tzu-Chiang CHEN
  • Patent number: 10290548
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung-Ying Lee, Szu-Wei Huang, Huan-Sheng Wei
  • Publication number: 20190139838
    Abstract: A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a second dielectric sheath layer, and a metal gate. The first gate dielectric layer is around the n-channel. The first dielectric sheath layer is around the first gate dielectric layer. The second gate dielectric layer is around the p-channel. The second dielectric sheath layer is around the second gate dielectric layer, in which the first dielectric sheath layer and the second dielectric sheath layer comprise different materials. The metal gate electrode is around the first dielectric sheath layer and the second dielectric sheath layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: I-Sheng CHEN, Tzu-Chiang CHEN, Cheng-Hsien WU, Chih-Chieh YEH, Chih-Sheng CHANG
  • Patent number: 10283414
    Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Chih-Sheng Chang, Cheng-Hsien Wu
  • Patent number: 10283639
    Abstract: A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen
  • Publication number: 20190131415
    Abstract: Present disclosure provides gate-all-around structure including a first transistor. The first transistor includes a semiconductor substrate having a top surface, a first nanowire over the top surface of the semiconductor substrate and between a first source and a first drain, a first gate structure around the first nanowire, an inner spacer between the first gate structure and the first source and first drain, and an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: CHAO-CHING CHENG, YU-LIN YANG, I-SHENG CHEN, TZU-CHIANG CHEN
  • Publication number: 20190131431
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Chao-Ching CHENG, Chen-Feng HSU, Tzu-Chiang CHEN, Tung Ying LEE, Wei-Sheng YUN, Yu-Lin YANG
  • Patent number: 10271601
    Abstract: The helmet has a cap, and a turning assembly and a fastening device assembled on the cap. The helmet is formed as an integral whole and has a simplified and compact structure. A camera is mounted to the fastening device and is held by a lower holder and an upper holder of the turning assembly. A locking panel of the fastening device allows the camera to be easily and quickly mounted onto the cap via the fastening device or removed from the fastening device. With a locking member engaging in or disengaging from one of multiple engaging recesses of a corresponding guiding rod of the turning assembly, a position of the camera relative to the cap can be also easily and quickly adjusted.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 30, 2019
    Inventor: Tzu-Chiang Chen
  • Publication number: 20190123189
    Abstract: A multi-gate semiconductor device includes a substrate, a stacked wire structure disposed over the substrate, a gate over the stacked wire structure, and at least a first spacer disposed over two sidewalls of the gate. The gate further includes a gate conductive structure wrapping the stacked wire structure and a gate dielectric layer sandwiched between the gate conductive structure and the stacked wire structure. Further, sidewalls of the gate conductive structure are in contact with the first spacer.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 25, 2019
    Inventors: I-SHENG CHEN, TZU-CHIANG CHEN, CHENG-HSIEN WU, LING-YEN YEH, CARLOS H. DIAZ
  • Publication number: 20190123163
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.
    Type: Application
    Filed: November 21, 2018
    Publication date: April 25, 2019
    Inventors: Yu-Lin YANG, Tung Ying LEE, Shao-Ming YU, Chao-Ching CHENG, Tzu-Chiang CHEN, Chao-Hsien HUANG
  • Patent number: 10269965
    Abstract: A multi-gate semiconductor device includes a substrate, a stacked wire structure disposed over the substrate, a gate over the stacked wire structure, and at least a first spacer disposed over two sidewalls of the gate. The gate further includes a gate conductive structure wrapping the stacked wire structure and a gate dielectric layer sandwiched between the gate conductive structure and the stacked wire structure. Further, sidewalls of the gate conductive structure are in contact with the first spacer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Ling-Yen Yeh, Carlos H. Diaz
  • Publication number: 20190109204
    Abstract: A method includes providing a substrate; forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench; forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench; depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches; recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; and forming a gate electrode layer over the gate dielectric layer in the first and second gate trenches.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, I-Sheng Chen, Shao-Ming Yu, Tzu-Chiang Chen, Chih Chieh Yeh
  • Publication number: 20190103267
    Abstract: A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions.
    Type: Application
    Filed: June 12, 2018
    Publication date: April 4, 2019
    Inventors: I-Sheng CHEN, Tzu-Chiang CHEN, Cheng-Hsien WU
  • Publication number: 20190103472
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, I-Sheng Chen, Shao-Ming Yu, Tzu-Chiang Chen, Chih Chieh Yeh
  • Publication number: 20190097053
    Abstract: A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: CHAO-CHING CHENG, CHEN-FENG HSU, YU-LIN YANG, JUNG-PIAO CHIU, TZU-CHIANG CHEN
  • Patent number: 10243433
    Abstract: A refrigerating machine having a detachable Hall element is provided with a cold heat exchange mechanism. The cold-heat exchange mechanism is driven by a driving assembly to generate a low temperature cooling zone at one end of the cold heat exchange mechanism. The driving assembly is composed of at least one rotor and a stator. After the power is input, the rotor can rotate a shaft to drive the cold-heat exchange mechanism to work. The driving assembly further has at least one Hall element and a circuit board on which the Hall element is mounted. Therefore, when the Hall element is damaged, the circuit board can be easily removed for replacement or repair.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 26, 2019
    Inventor: Tzu-Chiang Chen
  • Publication number: 20190067121
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN, Tung-Ying LEE, Szu-Wei HUANG, Huan-Sheng WEI