Patents by Inventor Tzu-Chieh Hsu

Tzu-Chieh Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200379323
    Abstract: A lens includes a casing, a first lens group, a second lens group and a heat dissipating member. The first lens group is disposed in the casing and close to a first side of the casing. The second lens group is disposed in the casing and close to a second side of the casing, wherein the first side is opposite to the second side. The heat dissipating member is disposed at the second side of the casing and contacts the casing.
    Type: Application
    Filed: April 26, 2020
    Publication date: December 3, 2020
    Inventors: Chien-Hung Lin, Tzu-Huan Hsu, Sheng-Wen Hu, Hsin-Jung Yeh, Chih-Chieh Tsung
  • Publication number: 20200350317
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200350113
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: Feng-Lung CHIEN, Tsang-Feng WU, Yuan HAN, Tzu-Chieh KAO, Chien-Hung LIN, Kuang-Lun LEE, Hsiang-Hui HSU, Shu-Yi TSUI, Kuo-Jui LEE, Kun-Ying LEE, Mao-Chun CHEN, Tai-Hsien YU, Wei-Yu CHEN, Yi-Ju LI, Kuei-Yuan CHANG, Wei-Chun LI, Ni-Ni LAI, Sheng-Hao LUO, Heng-Sheng PENG, Yueh-Hui KUAN, Hsiu-Chen LIN, Yan-Bing ZHOU, Chris T. Burket
  • Publication number: 20200301110
    Abstract: An optical imaging lens assembly includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements of the optical imaging lens assembly has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one lens element of the optical imaging lens assembly has at least one aspheric lens surface having at least one inflection point. The object-side surface of the seventh lens element is concave in a paraxial region thereof.
    Type: Application
    Filed: May 6, 2019
    Publication date: September 24, 2020
    Applicant: LARGAN PRECISION CO.,LTD.
    Inventors: Po-Lun HSU, Tzu-Chieh KUO
  • Publication number: 20200274022
    Abstract: A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Hsin-Chih Chiu, Chih-Chiang Lu, Chun-Yu Lin, Ching-Huai Ni, Yi-Ming Chen, Tzu-Chieh Hsu, Ching-Pei Lin
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200266199
    Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Patent number: 10685964
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Patent number: 10672667
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10651335
    Abstract: A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 12, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Chih Chiu, Chih-Chiang Lu, Chun-Yu Lin, Ching-Huai Ni, Yi-Ming Chen, Tzu-Chieh Hsu, Ching-Pei Lin
  • Publication number: 20200127027
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Publication number: 20200119225
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor stack, a trench formed in the semiconductor stack, a current confinement layer, a first electrode and a second electrode. The semiconductor stack includes a first reflective structure, a second reflective structure, and a cavity region. The cavity is between the first reflective structure and the second reflective structure and has a first surface and a second surface opposite to the first surface. The current confinement layer is in the second reflective structure. The first electrode and the second electrode are on the first surface.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Tzu-Chieh HSU, Yi-Wen HUANG, Shou-Lung CHEN, Hsin-Kang CHEN
  • Publication number: 20200066935
    Abstract: This disclosure discloses a light-emitting device. The light-emitting device includes a light-emitting stack having a first-type semiconductor layer, a second-type semiconductor layer, and an active layer formed between the first-type semiconductor layer and the second-type semiconductor layer; and a reflective structure formed on the first-type semiconductor layer and having a first interface and a second interface. A critical angle at the first interface for a light emitted from the light-emitting stack is larger than that at the second interface. The reflective structure electrically connects to the first-type semiconductor layer at the first interface, and an area of the first interface is more than an area of the second interface in a top view.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: Yi-Ming CHEN, Hao-Min KU, Chih-Chiang LU, Tzu-Chieh HSU
  • Publication number: 20200043803
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10553747
    Abstract: A semiconductor device comprises a substrate, a first semiconductor unit on the substrate, and an first adhesion structure between the substrate and the first semiconductor unit, and directly contacting the first semiconductor unit and the substrate, wherein the first adhesion structure comprises an adhesion layer and a sacrificial layer, and the adhesion layer and the sacrificial layer are made of different materials, and wherein an adhesion between the first semiconductor unit and the adhesion layer is different from that between the first semiconductor unit and the sacrificial layer.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 4, 2020
    Assignee: Epistar Corporation
    Inventors: Chih-Chiang Lu, Yi-Ming Chen, Chun-Yu Lin, Ching-Pei Lin, Chung-Hsun Chien, Chien-Fu Huang, Hao-Min Ku, Min-Hsun Hsieh, Tzu-Chieh Hsu
  • Publication number: 20200020729
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20200020698
    Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Tsun-Min Cheng, Chi-Mao Hsu
  • Patent number: 10535799
    Abstract: A semiconductor device includes a first reflective structure, a second reflective structure and a cavity region between the first reflective structure and the second reflective structure. The cavity region includes a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first electrode on the first surface and electrically connected to the first reflective structure. The semiconductor device further includes a second electrode on the first surface and electrically connected to the second reflective structure. The semiconductor device further includes a first conductive layer on the second surface of the cavity region and including a hole formed therethrough.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 14, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Tzu-Chieh Hsu, Yi-Wen Huang, Shou-Lung Chen, Hsin-Kang Chen
  • Patent number: 10535706
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Patent number: 10515994
    Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung, Min-Feng Kao