Patents by Inventor Tzu-Chieh Shen

Tzu-Chieh Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11511870
    Abstract: A parachute device for drone includes a container, a power source, a base, a parachute body and an open-assist member. A top of the container has an opening. The power source is disposed on a bottom of the container. The base is disposed on the power source. The parachute body, disposed on the base, is in a folded status. The open-assist member is disposed in the parachute body. The open-assist member contacts the base and the center of the inner surface of the parachute body.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: November 29, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tzu-Chieh Shen, Kuo-Hung Lin
  • Publication number: 20220317408
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Patent number: 11397302
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: July 26, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11372779
    Abstract: A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 28, 2022
    Assignees: Industrial Technology Research Institute, National Taiwan University
    Inventors: Che-Wei Tsao, Tei-Wei Kuo, Yuan-Hao Chang, Tzu-Chieh Shen, Shau-Yin Tseng
  • Publication number: 20220073209
    Abstract: A parachute device for drone includes a container, a power source, a base, a parachute body and an open-assist member. A top of the container has an opening. The power source is disposed on a bottom of the container. The base is disposed on the power source. The parachute body, disposed on the base, is in a folded status. The open-assist member is disposed in the parachute body. The open-assist member contacts the base and the center of the inner surface of the parachute body.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 10, 2022
    Inventors: TZU-CHIEH SHEN, KUO-HUNG LIN
  • Publication number: 20200201782
    Abstract: A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.
    Type: Application
    Filed: May 30, 2019
    Publication date: June 25, 2020
    Applicants: Industrial Technology Research Institute, National Taiwan University
    Inventors: Che-Wei Tsao, Tei-Wei Kuo, Yuan-Hao Chang, Tzu-Chieh Shen, Shau-Yin Tseng
  • Patent number: 10141266
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10068842
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 4, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20180247891
    Abstract: A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.
    Type: Application
    Filed: May 1, 2018
    Publication date: August 30, 2018
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Yu-Cheng Pai, Tzu-Chieh Shen
  • Patent number: 10043757
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: May 10, 2015
    Date of Patent: August 7, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10002825
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 19, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9905438
    Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ming-Chen Sun, Chun-Hsien Lin, Tzu-Chieh Shen, Shih-Chao Chiu, Yu-Cheng Pai
  • Patent number: 9899249
    Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170352615
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 7, 2017
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170309537
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170301658
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9785448
    Abstract: A system suspending method, a system resuming method and a computer system using the same are provided. The system resuming method of the computer system is applied for resuming the computer system to be a normal status (S0 status) from a suspend-to-ram status (S3 status) or a suspend-to-disk status (S4 status). The computer system includes a plurality of peripheral devices and a central processing unit. The peripheral devices are classified into a first group and a second group. The system resuming method includes the following steps. The central processing unit is powered on. Then, the peripheral devices belonging in the first group are resumed. Next, the computer system is thawed.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 10, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuo-Hung Lin, You-Ching Lin, Tzu-Chieh Shen
  • Publication number: 20170287840
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Application
    Filed: June 13, 2017
    Publication date: October 5, 2017
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170236725
    Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.
    Type: Application
    Filed: March 22, 2017
    Publication date: August 17, 2017
    Inventors: Ming-Chen Sun, Chun-Hsien Lin, Tzu-Chieh Shen, Shih-Chao Chiu, Yu-Cheng Pai
  • Patent number: 9735080
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: August 15, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen