Patents by Inventor Tzu-Chien Tzeng
Tzu-Chien Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11244621Abstract: A differential input circuit and a driving circuit including the same are provided. The differential input circuit transforms an analog voltage signal corresponding to a sensing line on an OLED panel to a pair of differential input signals being output to a gain amplifier. The differential input circuit includes a sampling circuit and a scaling circuit. The sampling circuit receives the analog voltage signal and a reference voltage through a first scaling path and a second scaling path, respectively. The scaling circuit includes a first scaling path and a second scaling path. The first scaling path and the second scaling path collectively generate the pair of differential input signals, based on a first shift voltage, a first scaled voltage, a second shift voltage, and a second scaled voltage. The first shift voltage is less than the second shift voltage.Type: GrantFiled: March 17, 2020Date of Patent: February 8, 2022Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Chieh-An Lin, Tzu-Chien Tzeng
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Publication number: 20210295775Abstract: A differential input circuit and a driving circuit including the same are provided. The differential input circuit transforms an analog voltage signal corresponding to a sensing line on an OLED panel to a pair of differential input signals being output to a gain amplifier. The differential input circuit includes a sampling circuit and a scaling circuit. The sampling circuit receives the analog voltage signal and a reference voltage through a first scaling path and a second scaling path, respectively. The scaling circuit includes a first scaling path and a second scaling path. The first scaling path and the second scaling path collectively generate the pair of differential input signals, based on a first shift voltage, a first scaled voltage, a second shift voltage, and a second scaled voltage. The first shift voltage is less than the second shift voltage.Type: ApplicationFiled: March 17, 2020Publication date: September 23, 2021Inventors: Chieh-An LIN, Tzu-Chien TZENG
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Patent number: 10789883Abstract: The disclosure provides a sensing apparatus and an operation method thereof. The sensing apparatus includes a sensing circuit, an analog-to-digital converter (ADC) circuit, a disturbing circuit and an output circuit. The sensing circuit is configured to output a sensing signal indicating a sensing result of a sensing line of the display panel. The ADC circuit is coupled to the sensing circuit to receive the sensing signal and outputs sensing data related to the sensing signal. The disturbing circuit is coupled to the ADC circuit to receive the sensing data and generates a time-variant disturbance component to disturb the sensing data to generate disturbed data. The output circuit is coupled to the disturbing circuit to receive the disturbed data.Type: GrantFiled: June 6, 2018Date of Patent: September 29, 2020Assignee: Novatek Microelectronics Corp.Inventors: Tzu-Chien Tzeng, Po-Hsiang Fang
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Patent number: 10725486Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.Type: GrantFiled: August 2, 2018Date of Patent: July 28, 2020Assignee: Novatek Microelectronics Corp.Inventors: Yong-Ren Fang, Shen-Iuan Liu, Ju-Lin Huang, Tzu-Chien Tzeng, Keko-Chun Liang, Yu-Hsiang Wang, Che-Wei Yeh
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Patent number: 10594264Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.Type: GrantFiled: June 28, 2018Date of Patent: March 17, 2020Assignee: NOVATEK Microelectronics Corp.Inventors: Cheng-En Hsieh, Shen-Iuan Liu, Tzu-Chien Tzeng, Jin-Yi Lin, Kuo-Sheng Huang, Ju-Lin Huang
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Publication number: 20200007085Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Cheng-En Hsieh, Shen-Iuan Liu, Tzu-Chien Tzeng, Jin-Yi Lin, Kuo-Sheng Huang, Ju-Lin Huang
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Patent number: 10476263Abstract: An electrostatic discharge (ESD) protection device and an operation method of the ESD protection device are provided. The ESD protection device includes an ESD current rail, an ESD protection element string, and a bias circuit. A first end and a second end of the ESD protection element string are electrically connected to the ESD current rail and a signal pad, respectively. The ESD protection element string includes a first ESD protection element and a second ESD protection element that are serially connected. The bias circuit is electrically connected to the ESD protection element string to provide a bias voltage to a common connection node between the first ESD protection element and the second ESD protection element.Type: GrantFiled: December 31, 2015Date of Patent: November 12, 2019Assignee: Novatek Microelectronics Corp.Inventors: Tzu-Chien Tzeng, Jie-Ting Chen, Chun-Yu Lin, Ming-Dou Ker
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Publication number: 20190130824Abstract: The disclosure provides a sensing apparatus and an operation method thereof. The sensing apparatus includes a sensing circuit, an analog-to-digital converter (ADC) circuit, a disturbing circuit and an output circuit. The sensing circuit is configured to output a sensing signal indicating a sensing result of a sensing line of the display panel. The ADC circuit is coupled to the sensing circuit to receive the sensing signal and outputs sensing data related to the sensing signal. The disturbing circuit is coupled to the ADC circuit to receive the sensing data and generates a time-variant disturbance component to disturb the sensing data to generate disturbed data. The output circuit is coupled to the disturbing circuit to receive the disturbed data.Type: ApplicationFiled: June 6, 2018Publication date: May 2, 2019Applicant: Novatek Microelectronics Corp.Inventors: Tzu-Chien Tzeng, Po-Hsiang Fang
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Publication number: 20190113939Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.Type: ApplicationFiled: August 2, 2018Publication date: April 18, 2019Applicant: Novatek Microelectronics Corp.Inventors: Yong-Ren Fang, Shen-Iuan Liu, Ju-Lin Huang, Tzu-Chien Tzeng, Keko-Chun Liang, Yu-Hsiang Wang, Che-Wei Yeh
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Patent number: 10256967Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.Type: GrantFiled: January 8, 2018Date of Patent: April 9, 2019Assignee: Novatek Microelectronics Corp.Inventors: Chang-Cheng Huang, Shen-Iuan Liu, Ju-Lin Huang, Tzu-Chien Tzeng, Keko-Chun Liang, Yu-Hsiang Wang, Che-Wei Yeh
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Patent number: 10147717Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.Type: GrantFiled: August 26, 2016Date of Patent: December 4, 2018Assignee: Novatek Microelectronics Corp.Inventors: Federico Agustin Altolaguirre, Ming-Dou Ker, Tzu-Chien Tzeng, Ju-Lin Huang
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Patent number: 10121777Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.Type: GrantFiled: September 26, 2016Date of Patent: November 6, 2018Assignee: Novatek Microelectronics Corp.Inventors: Chun-Yu Lin, Jie-Ting Chen, Ming-Dou Ker, Tzu-Chien Tzeng, Keko-Chun Liang, Ju-Lin Huang
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Publication number: 20180198597Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.Type: ApplicationFiled: January 8, 2018Publication date: July 12, 2018Applicant: Novatek Microelectronics Corp.Inventors: Chang-Cheng Huang, Shen-Iuan Liu, Ju-Lin Huang, Tzu-Chien Tzeng, Keko-Chun Liang, Yu-Hsiang Wang, Che-Wei Yeh
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Publication number: 20180159318Abstract: A power rail clamp circuit is coupled between a system power supply and a ground for alleviating an electrostatic discharge effect. The power rail clamp circuit includes a first conduction circuit, a second conduction circuit, an AND gate module and a switch module. The AND gate module receives a first conduction signal generated by the first conduction circuit and a second conduction signal generated by the second conduction circuit to generate an enabling signal. The switch module conducts the power rail clamp circuit according to the enabling signal, to process an electrostatic discharge operation. The first conduction circuit is operated to prevent a high voltage value of the system power supply, and the second conduction circuit is operated to prevent a short initiation period of the system power supply.Type: ApplicationFiled: December 7, 2016Publication date: June 7, 2018Inventors: Jie-Ting Chen, Chun-Yu Lin, Ming-Dou Ker, Ju-Lin Huang, Tzu-Chiang Lin, Tzu-Chien Tzeng
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Publication number: 20170309612Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.Type: ApplicationFiled: September 26, 2016Publication date: October 26, 2017Applicant: Novatek Microelectronics Corp.Inventors: Chun-Yu Lin, Jie-Ting Chen, Ming-Dou Ker, Tzu-Chien Tzeng, Keko-Chun Liang, Ju-Lin Huang
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Patent number: 9780085Abstract: An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.Type: GrantFiled: December 9, 2016Date of Patent: October 3, 2017Assignee: Novatek Microelectronics Corp.Inventors: Rong-Kun Chang, Jie-Ting Chen, Chun-Yu Lin, Ming-Dou Ker, Tzu-Chien Tzeng, Ping-Chang Lin
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Publication number: 20170194786Abstract: An electrostatic discharge (ESD) protection device and an operation method of the ESD protection device are provided. The ESD protection device includes an ESD current rail, an ESD protection element string, and a bias circuit. A first end and a second end of the ESD protection element string are electrically connected to the ESD current rail and a signal pad, respectively. The ESD protection element string includes a first ESD protection element and a second ESD protection element that are serially connected. The bias circuit is electrically connected to the ESD protection element string to provide a bias voltage to a common connection node between the first ESD protection element and the second ESD protection element.Type: ApplicationFiled: December 31, 2015Publication date: July 6, 2017Inventors: Tzu-Chien Tzeng, Jie-Ting Chen, Chun-Yu Lin, Ming-Dou Ker
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Publication number: 20170069618Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.Type: ApplicationFiled: August 26, 2016Publication date: March 9, 2017Applicant: Novatek Microelectronics Corp.Inventors: Federico Agustin Altolaguirre, Ming-Dou Ker, Tzu-Chien Tzeng, Ju-Lin Huang
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Patent number: 9008253Abstract: A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.Type: GrantFiled: February 23, 2013Date of Patent: April 14, 2015Assignee: NOVATEK Microelectronics Corp.Inventors: Tzu-Chien Tzeng, Hung-Yi Cheng
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Patent number: 8892617Abstract: A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes.Type: GrantFiled: November 27, 2008Date of Patent: November 18, 2014Assignee: Realtek Semiconductor Corp.Inventor: Tzu-Chien Tzeng