Patents by Inventor Tzu-Hung Lin

Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10348839
    Abstract: A device management method for use in a cloud system including a remote device, a mobile device and a cloud server is provided. The method includes the steps of: using, by the mobile device and the remote device, a same login information to log in the cloud server; sending, by the remote device, a push notification message to the mobile device through the cloud server when detecting that a first device is connected to a connection port, wherein the push notification message includes first identification information corresponding to the first device; and in response to receiving the push notification message, identifying, by the mobile device, the first device according to the first identification information to activate a respective application so as to perform data transmission with the first device through the respective application.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: July 9, 2019
    Assignee: ACER INCORPORATED
    Inventors: Cheng-Hung Chen, Chao-Kuang Yang, Wen-Cheng Hsu, Shih-Hao Lin, Chia-Hsun Lee, Chi-Hung Chang, Tzu-Kang Huang, Chen-Hsiang Ko, Chi-Sheng Lin
  • Patent number: 10332830
    Abstract: A semiconductor package assembly having a first semiconductor package, with a first redistribution layer (RDL) structure, a first semiconductor die having through silicon via (TSV) interconnects formed passing therethrough coupled to the first RDL structure, and a second semiconductor package stacked on the first semiconductor package with a second redistribution layer (RDL) structure. The assembly further includes a second semiconductor die without through silicon via (TSV) interconnects formed passing therethrough, coupled to the second RDL structure, and a third semiconductor package stacked on the second semiconductor package, having a third redistribution layer (RDL) structure, a third semiconductor die without through silicon via (TSV) interconnects formed passing therethrough coupled to the third RDL structure.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 25, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Wei-Che Huang, Tzu-Hung Lin
  • Publication number: 20190189496
    Abstract: A carrier structure suitable for transferring or supporting a plurality of micro devices including a carrier and a plurality of transfer units is provided. The transfer units are disposed on the carrier. Each of the transfer units includes a plurality of transfer parts. Each of the transfer parts has a transfer surface. Each of the micro devices has a device surface. The transfer surfaces of the transfer parts of each of the transfer units are connected to the device surface of corresponding micro device. The area of each of the transfer surfaces is smaller than the area of the device surface of the corresponding micro device. A micro device structure using the carrier structure is also provided.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 20, 2019
    Applicant: PixeLED Display CO., LTD.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li, Huan-Pu Chang, Chih-Ling Wu, Yu-Yun Lo, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20190189858
    Abstract: A display device including a backplane, a plurality of light-emitting devices, a first distributed Bragg reflector layer and a second distributed Bragg reflector layer is provided. The light-emitting devices are disposed on the backplane. The first distributed Bragg reflector layer is disposed between the backplane and the light-emitting devices. The light-emitting devices are disposed between the first distributed Bragg reflector layer and the second distributed Bragg reflector layer. A projected area of the first distributed Bragg reflector layer on the backplane is larger than a projected area of one of the light-emitting devices on the backplane or a projected area of the second distributed Bragg reflector layer on the backplane is larger than a projected area of one light-emitting device on the backplane.
    Type: Application
    Filed: February 25, 2019
    Publication date: June 20, 2019
    Applicant: PlayNitride Inc.
    Inventors: Yun-Li Li, Yu-Hung Lai, Tzu-Yang Lin
  • Patent number: 10325888
    Abstract: A manufacturing method of a display including the following steps is provided. Firstly, a back plate, a first transfer platform and a second transfer platform are provided, wherein a plurality of first light-emitting devices are disposed on the first transfer platform, and a plurality of second light-emitting devices are disposed on the second transfer platform. Secondly, a plurality of first bonding layers are formed at a plurality of first positions of the back plate. Then, the first transfer platform and the back plate are correspondingly docked, so that the first light-emitting devices are bonded on the first positions through the first bonding layers. After that, a plurality of second bonding layers are formed at a plurality of second positions of the back plate. Finally, the second transfer platform and the back plate are correspondingly docked, so that the second light-emitting devices are bonded on the second positions through the second bonding layers.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 18, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Tzu-Yang Lin, Yu-Yun Lo
  • Patent number: 10326045
    Abstract: A method for manufacturing a micro light emitting diode device is provided. A connection layer and epitaxial structures are formed on a substrate. A first pad is formed on each of the epitaxial structures. A first adhesive layer is formed on the connection layer, and the first adhesive layer encapsulates the epitaxial structures and the first pads. A first substrate is connected to the first adhesive layer. The substrate is removed, and a second substrate is connected to the connection layer through a second adhesive layer. The first substrate and the first adhesive layer are removed. The connection layer located between any two adjacent epitaxial structures are partially removed to form a plurality of connection portions. Each of the connection portions is connected to the corresponding epitaxial structure, and a side edge of each of the connection portions protrudes from a side wall surface of the corresponding epitaxial structure.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: June 18, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yu-Yun Lo, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20190154905
    Abstract: The electronic display device includes a display panel, an optical film unit, a first light source member, and a rear chassis assembly. The optical film unit and the first light source member are disposed corresponding to the display panel. The rear chassis assembly includes a substrate, a first side wall, a second side wall, and a bracket. The substrate has a front surface. The first side wall and the second side wall are respectively disposed on opposite sides of the substrate, and have substantially the same curvature. The bracket is disposed on the front surface of the substrate and has substantially the same curvature as the substrate. The bracket is disposed between the front surface of the substrate and the optical film unit.
    Type: Application
    Filed: January 24, 2019
    Publication date: May 23, 2019
    Inventors: Yung-Yu TSAI, Chin-Tu TSAI, Wen-Hung LEE, Ting-Yen LIN, Tzu-Yuan LIN
  • Patent number: 10297723
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: May 21, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Publication number: 20190148301
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Application
    Filed: February 28, 2018
    Publication date: May 16, 2019
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 10290622
    Abstract: A method for expanding spacings in a light-emitting element array includes the following steps of: providing a light-emitting element array unit including a stretchable supporting film, and a plurality of light-emitting elements disposed on the stretchable supporting film and arranged into a two-dimensional array; stretching the stretchable supporting film along a first direction and a second direction. The first direction and the second direction respectively correspond to a row direction and a column direction of the two-dimensional array.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 14, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yu-Chu Li, Yu-Hung Lai, Tzu-Yang Lin
  • Publication number: 20190131233
    Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
  • Patent number: 10256210
    Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 9, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 10217723
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 26, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
  • Patent number: 10217724
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 26, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Publication number: 20190043848
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Application
    Filed: July 24, 2018
    Publication date: February 7, 2019
    Inventors: Chia-Cheng CHANG, I-Hsuan PENG, Tzu-Hung LIN
  • Publication number: 20190043771
    Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
    Type: Application
    Filed: June 7, 2018
    Publication date: February 7, 2019
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU
  • Patent number: 10199318
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 5, 2019
    Assignee: MEDIATEK INC.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
  • Patent number: 10177125
    Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 8, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Publication number: 20180323127
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 8, 2018
    Applicant: MediaTek Inc.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Patent number: RE47419
    Abstract: A liquid crystal display device includes a support frame having a bottom wall, and a main surrounding wall extending upwardly from and formed integrally as one piece with the bottom wall. The bottom wall and the surrounding wall cooperatively define a receiving space. The bottom wall includes a first support disposed in the receiving space. The main surrounding wall includes a second support disposed in the receiving space and spacedly above the first support. A backlight module is supported on the first support. A liquid crystal display panel is supported on the second support so that the liquid crystal display panel is positioned above the backlight module.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 4, 2019
    Assignee: Wistron Corporation
    Inventors: Ching-Fu Hsu, Tzu-Wei Lin, Lien-Te Kao, Chi-Yeh Lu, Ming-Hung Pan, Ming-Chen Lin, Min-Wei Lin, Ting-Feng Chen, Wan-Bing Xia, Kai-Cheng Yen, Meng Zhang