Patents by Inventor Tzu-Hung Lin

Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200310243
    Abstract: The present disclosure provides a photomask, including a front side having a patterned layer, a back side opposite to the front side, a sidewall connecting the front side and the back side, a reflective layer between the front side and the back side, and a polymer layer on the backside of the photomask.
    Type: Application
    Filed: February 19, 2020
    Publication date: October 1, 2020
    Inventors: TZU HAN LIU, CHIH-WEI WEN, CHUNG-HUNG LIN
  • Publication number: 20200312732
    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 1, 2020
    Inventors: Yen-Yao CHI, Nai-Wei LIU, Ta-Jen YU, Tzu-Hung LIN, Wen-Sung HSU, Shih-Chin LIN
  • Publication number: 20200312663
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: October 1, 2020
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yi-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Publication number: 20200303352
    Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Patent number: 10784203
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 10784211
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 22, 2020
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
  • Publication number: 20200295233
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first contact layer on the first semiconductor layer; a second contact layer on the second semiconductor layer, wherein the first contact layer and the second contact layer comprise a metal material other than gold (Au) or copper (Cu); a first pad on the semiconductor stack; a second pad on the semiconductor stack.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Bo-Jiun HU, Tsung-Hsun CHIANG, Wen-Hung CHUANG, Kuan-Yi LEE, Yu-Ling LIN, Chien-Fu SHEN, Tsun-Kai KO
  • Publication number: 20200294948
    Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.
    Type: Application
    Filed: May 31, 2020
    Publication date: September 17, 2020
    Inventors: Tzu-Hung Lin, Thomas Matthew Gregorich
  • Patent number: 10775694
    Abstract: The present disclosure provides an apparatus for mounting a pellicle to a photomask, including a cover having a first side and a second side opposite to the first side, wherein the second side is configured to face the photomask, and an air pad disposed between the first side and the second side, wherein the air pad comprises a compartment filled with air.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzu Han Liu, Chih-Wei Wen, Chung-Hung Lin
  • Patent number: 10763393
    Abstract: A micro light emitting diode chip having a plurality of light-emitting regions, including a semiconductor epitaxial structure, a first electrode and a plurality of second electrodes disposed at interval is provided. The semiconductor epitaxial structure includes a first-type doped semiconductor layer, a plurality of second-type doped semiconductor layers and a plurality of light-emitting layers disposed at interval. The light-emitting layers are located between the first-type doped semiconductor layer and the second-type doped semiconductor layer. The light-emitting layers are located in the light-emitting regions respectively and electrically contact to the first-type doped semiconductor layer. The first electrode is electrically connected and contacts to the first-type doped semiconductor layers. The second electrodes are electrically connected to the second-type doped semiconductor layers. Furthermore, a display panel is also provided.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 1, 2020
    Assignee: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Yu-Yun Lo, Tzu-Yang Lin
  • Publication number: 20200273812
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.
    Type: Application
    Filed: May 13, 2020
    Publication date: August 27, 2020
    Inventors: Tzu-Hung LIN, Yung-Chang LIEN
  • Publication number: 20200273737
    Abstract: A micro LED carrier board is provided. The micro LED carrier board includes a substrate structure having a first surface and a second surface and having a central region and a peripheral region on the outside of the central region. The micro LED carrier board includes a plurality of micro LED elements forming an array and on the second surface of the substrate structure. The micro LED carrier board includes a patterned structure formed on the first surface and the second surface. The patterned structure has a first pattern density in the central region and a second pattern density in the peripheral region, and the first pattern density is different from the second pattern density.
    Type: Application
    Filed: December 19, 2019
    Publication date: August 27, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Pei-Hsin CHEN, Yi-Ching CHEN, Yu-Chu LI, Yi-Chun SHIH, Ying-Tsang LIU, Yu-Hung LAI, Tzu-Yang LIN
  • Patent number: 10749075
    Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer; a plurality of first trenches penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer; a second trench penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer, wherein the second trench is disposed near an outmost edge of the active layer, and surrounds the active layer and the plurality of first trenches; a patterned metal layer formed on the second semiconductor layer and formed in one of the plurality of first trenches or the second trench; and a first pad portion and a second pad portion both formed on the second semiconductor layer and electrically connecting the second semiconductor layer and the first semiconductor layer respectively.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 18, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Tsung-Hsun Chiang, Bo-Jiun Hu, Wen-Hung Chuang, Yu-Ling Lin
  • Patent number: 10727202
    Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 28, 2020
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yu-Hua Huang, Wei-Che Huang, Ming-Tzong Yang
  • Patent number: 10707183
    Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 7, 2020
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Thomas Matthew Gregorich
  • Publication number: 20200211944
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: Tzu-Hung LIN, Yuan-Chin LIU
  • Patent number: 10692789
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: June 23, 2020
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Publication number: 20200185360
    Abstract: A micro LED display device including a display substrate, a plurality of conductive pad pairs and a plurality of micro light emitting elements is provided. The display substrate has a first arranging area, a splicing area connected to the first arranging area, and a second arranging area connected to the splicing area, wherein the splicing area is located between the first arranging area and the second arranging area. The conductive pad pairs are disposed on the display substrate in an array with the same pitch. The micro light emitting elements are disposed on the display substrate and are electrically bonded to the conductive pad pairs. A manufacturing method of the micro LED display device is also provided.
    Type: Application
    Filed: November 8, 2019
    Publication date: June 11, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Sheng-Yuan Sun, Ying-Tsang Liu, Yi-Ching Chen, Pei-Hsin Chen, Yi-Chun Shih, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20200185243
    Abstract: A carrier structure suitable for transferring or supporting a plurality of micro devices includes a carrier and a plurality of transfer units. The carrier has a carrier surface and a plurality of recesses disposed on the carrier surface. The transfer units are respectively disposed in the recesses and a plurality of transferring surfaces are exposed. Each micro device has a device surface. The transferring surface of each transfer unit is configured to be connected to the device surface of the corresponding micro device. A micro device structure including the carrier structure is also provided.
    Type: Application
    Filed: September 25, 2019
    Publication date: June 11, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li, Huan-Pu Chang, Tzu-Yang Lin, Yu-Hung Lai
  • Patent number: 10680138
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 9, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko