Patents by Inventor Tzu-Li Lee

Tzu-Li Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357914
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 10777510
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 10727344
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Publication number: 20200075427
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN, Tung-Ying LEE, Szu-Wei HUANG, Huan-Sheng WEI
  • Publication number: 20190267292
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes first semiconductor wires over a semiconductor substrate. The first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure also includes a gate stack surrounding first portions of the first semiconductor wires, and a spacer element surrounding second portions of the first semiconductor wires. The first portions have a first width and the second portions have a second width. In addition, the semiconductor device structure includes a second semiconductor wire between the second portions. The second semiconductor wire has a third width, and the third width is substantially equal to the second width and greater than the first width.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung-Ying Lee, Szu-Wei Huang, Huan-Sheng Wei
  • Patent number: 10290548
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung-Ying Lee, Szu-Wei Huang, Huan-Sheng Wei
  • Publication number: 20180151511
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Application
    Filed: January 3, 2017
    Publication date: May 31, 2018
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 8988652
    Abstract: A method and apparatus for ultraviolet (UV) and extreme ultraviolet (EUV) lithography patterning is provided. A UV or EUV light beam is generated and directed to the surface of a substrate disposed on a stage and coated with photoresist. A laminar flow of a layer of inert gas is directed across and in close proximity to the substrate surface coated with photoresist during the exposure, i.e. lithography operation. The inert gas is exhausted quickly and includes a short resonance time at the exposure location. The inert gas flow prevents flue gasses and other contaminants produced by outgassing of the photoresist, to precipitate on and contaminate other features of the lithography apparatus.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Hao Chang, Tsiao-Chen Wu, Chia-Hao Hsu, Chia-Chen Chen, Ying-Yu Chen, Tzu-Li Lee, Shang-Chieh Chien, Jeng-Horng Chen, Anthony Yen
  • Patent number: 8848374
    Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hong Lin, Chin Chuan Peng, Tzu-Li Lee, Bi-Ling Lin, Bor-Jou Wei, Chien Shih Tsai
  • Publication number: 20140111781
    Abstract: A method and apparatus for ultraviolet (UV) and extreme ultraviolet (EUV) lithography patterning is provided. A UV or EUV light beam is generated and directed to the surface of a substrate disposed on a stage and coated with photoresist. A laminar flow of a layer of inert gas is directed across and in close proximity to the substrate surface coated with photoresist during the exposure, i.e. lithography operation. The inert gas is exhausted quickly and includes a short resonance time at the exposure location. The inert gas flow prevents flue gasses and other contaminants produced by outgassing of the photoresist, to precipitate on and contaminate other features of the lithography apparatus.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao CHANG, Tsiao-Chen WU, Chia-Hao HSU, Chia-Chen CHEN, Ying-Yu CHEN, Tzu-Li LEE, Shang-Chieh CHIEN, Jeng-Horng CHEN, Anthony YEN
  • Patent number: 8541264
    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8354346
    Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: January 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
  • Publication number: 20120276732
    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8242576
    Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8212330
    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: July 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jian-Hong Lin, Tzu-Li Lee
  • Publication number: 20120002375
    Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong LIN, Chin Chuan PENG, Tzu-Li LEE, Bi-Ling LIN, Bor-Jou WEI, Chien Shih TSAI
  • Publication number: 20110263127
    Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
    Type: Application
    Filed: July 8, 2011
    Publication date: October 27, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
  • Patent number: 7998873
    Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: August 16, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
  • Publication number: 20100327456
    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jian-Hong Lin, Tzu-Li Lee
  • Patent number: 7816256
    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: October 19, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jian-Hong Lin, Tzu-Li Lee