Abstract: A dry etching method for reducing fluorocarbon-containing gas emissions is provided. The method includes supplying a first gas to a reaction chamber to adjust a process parameter related to the reaction chamber. The method also includes supplying a second gas to the reaction chamber. The method further includes turning on a power source to ionize the second gas, thereby generating plasma. The plasma is used to remove part of a material layer on a substrate. The composition of the first gas is different from the composition of the second gas.

Abstract: Provided is a memory device including a substrate, a plurality of bit-line structures, a plurality of conductive plugs, and a plurality of conductive pads. The substrate has a plurality of active areas. The plurality of bit-line structures are disposed on the substrate in parallel. The plurality of conductive plugs are respectively disposed aside the plurality of bit-line structures, and are electrically connected to the plurality of active areas. The plurality of conductive pads are vertically disposed between the plurality of conductive plugs and the plurality of active areas. One of the conductive plugs has a bottom area falls within a range of a top area of a corresponding conductive pad.

Abstract: A method for forming a semiconductor structure includes forming strip patterns over a semiconductor substrate, forming a hard mask layer over the strip patterns, and forming a patterned photoresist layer over the hard mask layer. The patterned photoresist layer has a plurality of first openings. The method also includes etching the hard mask layer using the patterned photoresist layer. Remaining portions of the hard mask layer form a plurality of pillar patterns that are separated from one another. The method also includes depositing a dielectric layer along the plurality of pillar patterns, etching the dielectric layer to form a plurality of second openings, removing the plurality of pillar patterns to form a plurality of third openings in the dielectric layer, and etching the strip patterns using the dielectric layer as a mask.

Abstract: The method of forming the semiconductor structure includes the following steps. Bit line structures are formed on a substrate. A first liner is formed on the bit line structures. A second liner is formed on the first liner. A portion of the second liner is removed to expose a portion of the top surface of the first liner. A portion of the first liner is removed to form a space between each bit line structure and the second liner and form a remaining first liner. A sealing material is formed at the opening of the space to form an air gap between each bit line structure and the second liner.

Abstract: Provided is a memory device and a method of forming the same. The method includes: providing a substrate having multiple active regions; forming a first layer stack on the substrate; patterning the first layer stack to form multiple recesses in the first layer stack; forming a liner layer on the first layer stack to cover the recesses; performing an etching process to remove a portion of the liner layer and the first layer stack below the recesses, so as to extend the recesses downward to form multiple openings, wherein the openings respectively expose the active regions; respectively forming multiple conductive structures in the openings; forming a second layer stack on the conductive structures; and patterning the second layer stack and the conductive structures to form multiple bit-line structures and bit-line contacts, respectively.

Abstract: A method for forming a semiconductor memory structure includes the following steps. A first patterned hard mask layer is formed over a conductive material. The first patterned hard mask layer includes first strip patterns and a mesa pattern. The mesa pattern is connected with the first strip patterns. A second patterned hard mask layer is formed over the first patterned hard mask layer. The second patterned hard mask layer includes second strip patterns overlapping the first strip patterns and first wire patterns overlapping the mesa pattern. The first patterned hard mask layer is etched using the second patterned hard mask layer. The remaining portions of the first strip patterns form pad patterns. The remaining portions of the mesa pattern form second wire patterns. The pad patterns and the second wire patterns are transferred into the conductive material.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A method for manufacturing a semiconductor device includes forming contacts disposed in a dielectric layer. The method of forming the contacts includes forming contact holes and then filling with a conductive material. The method of forming the contact holes includes steps of forming openings in the dielectric layer to expose active regions, introducing a first oxygen plasma and a first fluorine plasma to remove by-products and oxidize inner surfaces of the openings, introducing a second oxygen plasma and a second fluorine plasma to remove the oxidized inner surfaces and repair the active regions, introducing a third oxygen plasma to oxidize inner surfaces again to form an oxide layer, and removing the oxide layer. The cross-sectional structure of two adjacent contact holes includes a capital, a base, and a shaft between the capital and the base, wherein the shaft has a smaller width than the base and the capital.

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Abstract: A method for forming a semiconductor memory structure includes forming a plurality of conductive wire structures over a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each of the spacer structures includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips over the conductive wire structures and the dielectric strips, performing a patterning process on the conductive strips to form a plurality of conductive pads, and removing the first spacer of each of the spacer structures to form a gap in each of the spacer structures.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

Abstract: A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

Abstract: Provided is a DRAM including: a substrate, a plurality of chop structures, and a plurality of buried word lines. The plurality of chop structures are located in the substrate. Each of the plurality of chop structures comprises a first portion and a second portion. The first portion is located above the second portion, and a width of the second portion is less than a width of the first portion. The plurality of buried word lines, located at bottoms of a plurality of buried word line trenches. The plurality of buried word line trenches passes through the first portion of the plurality of chop structures and the substrate.

Abstract: Provided is a method of manufacturing a DRAM. A plurality of openings are formed in the substrate. A hard mask is formed on the sidewall of an upper part of each opening. The substrate and the hard mask are partially removed to form a plurality of isolation trenches and to define active regions. Each active region is located between the isolation trenches and remaining portions of the hard mask are located on two sides of each active region. The isolation trenches and the openings are filled with a dielectric layer. The substrate and the dielectric layer are partially removed to form a plurality of buried word line trenches. Each buried word line trench extends along a third direction and passes through the active regions, the openings and the isolation trenches. A plurality of buried word lines are formed in the buried word line trenches.