Patents by Inventor Tzung-Ting Han

Tzung-Ting Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515319
    Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 29, 2022
    Assignee: Macronix International Co., Ltd.
    Inventors: Chen-Yu Cheng, Tzung-Ting Han
  • Publication number: 20220302168
    Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Patent number: 11411020
    Abstract: Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 9, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Publication number: 20220199134
    Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chen-Yu Cheng, Tzung-Ting Han
  • Publication number: 20220173040
    Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 2, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
  • Publication number: 20220165747
    Abstract: A three-dimensional memory device and a method of manufacturing a three-dimensional memory device are provided. The method includes providing a precursor structure including a substrate, a multi-layered stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are then formed in the multi-layered stack and the substrate along a first direction, in which the first slit and the second slit have a pitch between thereof, and the second slit cuts the barrier structure. A portion of the second insulating layers is then replaced with a plurality of conductive layers. A first slit structure and a second slit structure are then formed in the first slit and the second slit, in which the first slit structure and the second slit structure separate the vertical channel pillars in a second direction that is different from the first direction.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Chih-Kai YANG, Tzung-Ting HAN
  • Publication number: 20220123009
    Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chien-Ying Lee, Chih-Hsiung Lee, Tzung-Ting Han
  • Publication number: 20210351196
    Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Applicant: Macronix International Co., Ltd.
    Inventors: Chen-Yu Cheng, Tzung-Ting Han
  • Publication number: 20210335801
    Abstract: Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Patent number: 11127756
    Abstract: Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 21, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Publication number: 20210020650
    Abstract: Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Applicant: MACRONIX International Co., Ltd.
    Inventors: CHIH-KAI YANG, Tzung-Ting Han
  • Publication number: 20190198630
    Abstract: Methods of managing gate coupling for semiconductor devices, e.g., non-volatile memory devices, are provided. The methods include: providing a conductive layer on a semiconductor substrate, the conductive layer including a lower conductive layer and an upper conductive layer, the lower conductive layer including a first material and the upper conductive layer including a second material having at least one property different from the first material, forming a protective pattern on the conductive layer, and etching through the conductive layer to obtain individual separated gates by controlling an etching process such that the first material has a higher etching rate than the second material during the etching process, each of the gates including an upper gate and a lower gate, the lower gate having a smaller width than the upper gate after the etching process.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Applicant: Macronix International Co., Ltd.
    Inventors: Chien-Ying Lee, Chih-Hsiung Lee, Tzung-Ting Han
  • Patent number: 10304680
    Abstract: Methods of fabricating semiconductor devices having patterns with different feature sizes are provided. An example method includes: etching a first film layer below a patterned mask to form first and second features on a second film layer, forming respective first and second spacers adjacent to sidewalls of the first and second features on the second film layer, removing the first and second features to expose respective first and second portion of the second film layer, the second portion having a larger CD than the first portion, controlling an etching process such that the first portion is etched through and the second portion is protected from etching by a protective film formed during the etching process, and patterning a thin film masked by the first spacer, the second spacer, and the second portion to form smaller features and larger features in respective first and second regions of the thin film.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 28, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Hsiung Lee, Tzung-Ting Han
  • Patent number: 10290543
    Abstract: A method for manufacturing semiconductor device is provided. A substrate having a memory region and a capacitance region is provided. A plurality of word line structures are formed on the memory region of the substrate. A capacitance structure is formed on the capacitance region of the substrate. The word line structures and the capacitance structure each include a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer, and a second conductive layer on the second dielectric layer. The second conductive layers of the word line structures close to an edge of the memory region and a portion of the second conductive layer of the capacitance structure are removed at the same time to form a trench exposing a portion of the second dielectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 14, 2019
    Assignee: MACRONXI International Co., Ltd.
    Inventors: Chang-Wen Jian, Hsiang-Lu Wu, Yu-Min Hung, Tzung-Ting Han
  • Publication number: 20180366573
    Abstract: A semiconductor device, a memory device, and a manufacturing method of the same are provided. The memory device includes a substrate, a floating gate, a gate insulation layer, an inter-gate dielectric layer, and a control gate. The control gate is a multi-layer structure with three or more layers, and at least one layer of the multi-layer structure is a metal silicide layer.
    Type: Application
    Filed: June 15, 2017
    Publication date: December 20, 2018
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Fu-Hsing Chou, Yao-Fu Chan, Tzung-Ting Han
  • Patent number: 9899396
    Abstract: A method for fabricating a semiconductor device includes: forming a first trench and a wider second trench in a substrate and a material layer formed thereon, forming a flowable isolation material covering the material layer and filling in the first and second trenches, removing a portion of the flowable isolation material in the second trench so that the thickness of the remaining flowable isolation material on the sidewall of the second trench is 200 ? to 1000 ?, and forming a non-flowable isolation material on the flowable isolation material.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 20, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Hsiung Lee, Chien-Ying Lee, Tzung-Ting Han
  • Patent number: 9847339
    Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 19, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Min Hung, Chien-Ying Lee, Tzung-Ting Han
  • Publication number: 20170294442
    Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Yu-Min Hung, Chien-Ying Lee, Tzung-Ting Han
  • Patent number: 9748332
    Abstract: A semiconductor device includes a semiconductor substrate, multiple memory cells on the semiconductor substrate arranged along a first dimension and along a second dimension that is orthogonal to the first dimension, in which each memory cell of the multiple memory cells includes a channel region in the semiconductor substrate, a tunnel dielectric layer on the channel region, and a first electrode layer on the tunnel dielectric layer. Along the first dimension, the channel region of each memory cell of the multiple memory cells is separated from the channel region of an adjacent memory cell of the multiple memory cells by a corresponding first air gap, each first air gap extending from below an upper surface of the semiconductor substrate up to an inter-electrode dielectric layer.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 29, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Kai Yang, Chen Yu Cheng, Shih Chin Lee, Ching Hung Wang, Tzung-Ting Han
  • Patent number: RE46970
    Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: July 24, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen