Abstract: A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.

Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Abstract: Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.

Abstract: This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.

Abstract: Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.

Abstract: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

Abstract: This invention provides a method for forming a microcrystalline polysilicon layer by using silane or dislane with introducing hydrogen gas. This microcrystalline polysilicon layer can be used as a floating gate of a flash memory to improve the character of the flash memory.

Abstract: Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.

Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.

Abstract: A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

Abstract: A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.

Abstract: A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.

Abstract: A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

Abstract: This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Abstract: Dual spacer structures are fabricated such that sidewall spacers in a cell region are thinner than sidewall spacers in a periphery region. The fabricating method of memory includes forming a stop layer over the first semiconductor feature and the second semiconductor feature in cell region and periphery region. A spacer layer is formed over the stop layer in the periphery region. The spacer layer is patterned to form a spacer on a sidewall of the second semiconductor feature. An etching process is performed to form a resultant spacer on an interior sidewall of the opening between first semiconductor features. The stop layer on top surfaces of the first and second semiconductor features is removed.