Patents by Inventor Uday Savagaonkar

Uday Savagaonkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10262162
    Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Uday Savagaonkar, Ravi L. Sahita
  • Patent number: 10181027
    Abstract: Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a processor, a device, and an interface plug-in. The processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to create a secure processing environment. The execution unit is to execute an application in the secure processing environment. The device is to execute a workload for the application. The interface plug-in is to provide an interface for the device to enter the secure processing environment to execute the workload.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Alpa Narendra Trivedi, Siddhartha Chhabra, Xiaozhu Kang, Prashant Dewan, Uday Savagaonkar, David Durham
  • Patent number: 10110374
    Abstract: In general, in one aspect, noise is injected into a bitmap associated with content to be presented on a display to create a noisy bitmap. The noisy bitmap is encrypted using electronic code book (ECB) encryption. The resulting ciphertext does not include recognizable patterns from the content as is typical with ECB encryption. The injection of noise may include modifying pixel values for at least a subset of pixels in the bitmap. The pixel values may be modified by using a counter, a known modification pattern, or a random number generator. The bitmap may be analyzed to determine how the bitmap can be modified to maximize the randomness of the bitmap while ensuring that the noisy bitmap is visually perceptually similar when presented. The noise may be injected into a block of pixels prior to the block being encrypted.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Scott Janus, Jason Martin, Uday Savagaonkar
  • Patent number: 9971705
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Publication number: 20180067758
    Abstract: Systems and methods are described herein that discuss how a computing platform executing a virtualized environment, in one example, can be integrity verified adaptively and on demand. This may occur at initial runtime, as well as during continued operations, and allows the platform user to install software from various vendors without sacrificing the integrity measurement and therefore the trustworthiness of the platform.
    Type: Application
    Filed: July 12, 2017
    Publication date: March 8, 2018
    Inventors: Ravi L. Sahita, Uday Savagaonkar
  • Publication number: 20170372063
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for virtualization-based intra-block workload isolation. The system may include a virtual machine manager (VMM) module to create a secure virtualization environment or sandbox. The system may also include a processor block to load data into a first region of the sandbox and to generate a workload package based on the data. The workload package is stored in a second region of the sandbox. The system may further include an operational block to fetch and execute instructions from the workload package.
    Type: Application
    Filed: July 21, 2017
    Publication date: December 28, 2017
    Applicant: Intel Corporation
    Inventors: PRASHANT DEWAN, UTTAM SENGUPTA, SIDDHARTHA CHHABRA, DAVID DURHAM, XIAOZHU KANG, UDAY SAVAGAONKAR, ALPA NARENDRA TRIVEDI
  • Patent number: 9852301
    Abstract: Embodiments of an invention for establishing secure channels between a protected execution environment and fixed-function endpoints are disclosed. In one embodiment, and system includes an architecturally protected memory, a processing core communicatively coupled to the architecturally protected memory, and a key distribution engine. The processing core is to implement an architecturally-protected execution environment by performing at least one of executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Alpa Narendra Trivedi, Siddhartha Chhabra, Uday Savagaonkar, Men Long
  • Publication number: 20170293775
    Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 12, 2017
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Uday Savagaonkar, Ravi L. Sahita
  • Patent number: 9729309
    Abstract: Embodiments of an invention for securing transmissions between processor packages are disclosed. In one embodiment, an apparatus includes an encryption unit to encrypt first content to be transmitted from the apparatus to a processor package directly through a point-to-point link.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Simon Johnson, Abhishek Das, Carlos Rozas, Uday Savagaonkar, Robert Blankenship, Kiran Padwekar
  • Patent number: 9710293
    Abstract: Systems and methods are described herein that discuss how a computing platform executing a virtualized environment, in one example, can be integrity verified adaptively and on demand. This may occur at initial runtime, as well as during continued operations, and allows the platform user to install software from various vendors without sacrificing the integrity measurement and therefore the trustworthiness of the platform.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Ravi Sahita, Uday Savagaonkar
  • Patent number: 9698989
    Abstract: Embodiments of an invention for feature licensing in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to initialize a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes determining whether a requested feature is licensed for use in the secure enclave.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Vincent Scarlata, Carlos Rozas, Simon Johnson, Uday Savagaonkar, Ittai Anati, Francis McKeen, Michael Goldsmith
  • Patent number: 9684511
    Abstract: In an embodiment, the present invention includes a processor having a decode unit, an execution unit, and a retirement unit. The decode unit is to decode control transfer instructions and the execution unit is to execute control transfer instructions. The retirement unit is to retire a first control transfer instruction, and to raise a fault if a next instruction to be retired after the first control transfer instruction is not a second control transfer instruction and a target instruction of the first control transfer instruction is in code using the control transfer instructions.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason Brandt, Uday Savagaonkar, Ravi Sahita
  • Publication number: 20170070342
    Abstract: In general, in one aspect, noise is injected into a bitmap associated with content to be presented on a display to create a noisy bitmap. The noisy bitmap is encrypted using electronic code book (ECB) encryption. The resulting ciphertext does not include recognizable patterns from the content as is typical with ECB encryption. The injection of noise may include modifying pixel values for at least a subset of pixels in the bitmap. The pixel values may be modified by using a counter, a known modification pattern, or a random number generator. The bitmap may be analyzed to determine how the bitmap can be modified to maximize the randomness of the bitmap while ensuring that the noisy bitmap is visually perceptually similar when presented. The noise may be injected into a block of pixels prior to the block being encrypted.
    Type: Application
    Filed: November 17, 2016
    Publication date: March 9, 2017
    Inventors: Scott Janus, Jason Martin, Uday Savagaonkar
  • Patent number: 9531916
    Abstract: In general, in one aspect, noise is injected into a bitmap associated with content to be presented on a display to create a noisy bitmap. The noisy bitmap is encrypted using electronic code book (ECB) encryption. The resulting ciphertext does not include recognizable patterns from the content as is typical with ECB encryption. The injection of noise may include modifying pixel values for at least a subset of pixels in the bitmap. The pixel values may be modified by using a counter, a known modification pattern, or a random number generator. The bitmap may be analyzed to determine how the bitmap can be modified to maximize the randomness of the bitmap while ensuring that the noisy bitmap is visually perceptually similar when presented. The noise may be injected into a block of pixels prior to the block being encrypted.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Scott Janus, Jason Martin, Uday Savagaonkar
  • Publication number: 20160188889
    Abstract: Embodiments of an invention for establishing secure channels between a protected execution environment and fixed-function endpoints are disclosed. In one embodiment, and system includes an architecturally protected memory, a processing core communicatively coupled to the architecturally protected memory, and a key distribution engine. The processing core is to implement an architecturally-protected execution environment by performing at least one of executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Alpa NARENDRA TRIVEDI, Siddhartha CHHABRA, Uday SAVAGAONKAR, Men LONG
  • Publication number: 20160170900
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Applicant: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Patent number: 9355262
    Abstract: Embodiments of an invention for modifying memory permissions in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to modify access permissions for a page in a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes setting new access permissions in an enclave page cache map entry. Furthermore, the page is immediately accessible from inside the secure enclave according to the new access permissions.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Rebekah Leslie-Hurd, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael Goldsmith, Simon Johnson, Francis McKeen, Carlos Rozas, Uday Savagaonkar, Vincent Scarlata, Vedvyas Shanbhogue, Wesley Smith
  • Publication number: 20160110540
    Abstract: Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a processor, a device, and an interface plug-in. The processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to create a secure processing environment. The execution unit is to execute an application in the secure processing environment. The device is to execute a workload for the application. The interface plug-in is to provide an interface for the device to enter the secure processing environment to execute the workload.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Applicant: Intel Corporation
    Inventors: ALPA NARENDRA TRIVEDI, Siddhartha Chhabra, Xiaozhu Kang, Prashant Dewan, Uday Savagaonkar, David Durham
  • Patent number: 9286235
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Patent number: 9276750
    Abstract: Embodiments of an invention for secure processing environment measurement and attestation are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction associated with a build or a rebuild of a secure enclave. The execution unit is to execute the first instruction. Execution of the first instruction, when associated with the build, includes calculation of a first measurement and a second measurement of the secure enclave. Execution of the first instruction, when associated with the rebuild, includes calculation of the second measurement without calculation of the first measurement.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Vincent R. Scarlata, Carlos Rozas, Simon Johnson, Uday Savagaonkar, Rebekah Leslie-Hurd, Barry Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis McKeen, Michael Goldsmith, William Wood, Shay Gueron