Patents by Inventor Uday Savagaonkar

Uday Savagaonkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7757035
    Abstract: In a virtualized processor based system causing a transition to a virtual machine monitor executing on the processor based system in response to a modification of a page table of a guest executing in a virtual machine of the processor based system, and the virtual machine monitor responding to the transition by performing a verification action, and for each bit modified in the page table of the guest, reading a status indicator for the bit to determine if the bit is significant; and causing the transition only if the status indicator for any bit modified in the page table indicates that the bit is significant.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: David Durham, Hormuzd Khosravi, Gayathri Nagabhushan, Uday Savagaonkar
  • Patent number: 7748037
    Abstract: A system and process are described to enable at least one of a plurality of host agents executing on a system to update memory region types of a system memory, register the at least one host agent in a registry stored in system management memory, receive a system management interrupt (SMI) from one of the plurality of host agents to update a memory region type, determine if the host agent issuing the SMI is listed in the registry stored in system management memory, update the memory region in response to determining the host agent issuing the SMI is listed in the registry, and maintain the memory region type in response to determining the host agent issuing the SMI is not listed in the registry.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Priya Rajagopal, Uday Savagaonkar, David Durham, Ravi Sahita, Hormuzd Khosravi
  • Patent number: 7624242
    Abstract: An embodiment of the present invention is a technique to protect memory. A memory identifiers storage stores memory identifiers associated with protected components. The memory identifiers include exclusive memory identifiers and shared memory identifiers. The memory identifier storage is protected from access by a host operating system. A memory identifier management service (MMS) manages the memory identifiers. The MMS resides in a protected environment. An access control enforcer (ACE) enforces an access control policy with the memory identifiers.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 24, 2009
    Assignee: Intel Corporation
    Inventors: Uday Savagaonkar, Ravi Sahita, Hormuzd Khosravi, Priya Rajagopal
  • Patent number: 7587612
    Abstract: Provided is a method, system, and program for generating and communicating information on locations of program sections in memory. Source code is generated for an agent program. The source code includes start and end variables for selected sections of the program, wherein the start and end variables for each selected section are used to indicate the start and end address in a memory at which the section is loaded. The selected sections are capable of including less than all the sections in the program. The source code is compiled and linked to generate an object file including the sections. The object file causes, in response to being loaded into the memory of a computer, a relocation of at least one of the start and end memory addresses of the selected sections into at least one of the start and end variables for the selected sections when memory addresses are assigned to sections as part of relocation operations. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: Uday Savagaonkar, Travis Schluessler
  • Publication number: 20090220090
    Abstract: An apparatus and system provide a tamper-resistant scheme for portability of DRM-protected digital content. According to embodiments of the invention, a portable crypto unit may be utilized in conjunction with a VT integrity services (VIS) scheme as well as a Virtual Machine Manager (VMM) and a TPM to provide a secure scheme to protect digital content. Additionally, in one embodiment, the digital content may be partitioned into blocks comprising multiple segments to further enhance the security of the scheme.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Inventors: Uday Savagaonkar, Prashant Dewan, Men Long
  • Patent number: 7571298
    Abstract: Systems and methods are described herein to provide for host virtual memory reconstitution. Virtual memory reconstitution is the ability to translate the host device's virtual memory addresses to the host device's physical memory addresses. The virtual memory reconstitution methods are independent of the operating system running on the host device.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventors: Hormuzd M. Khosravi, David M. Durham, Travis Schluessler, Ravi Sahita, Uday Savagaonkar, Priya Rajagopal
  • Publication number: 20090172663
    Abstract: A method to communicate information between components in a virtualization enabled platform. In one embodiment, a component exchanges data via a communication page which only integrity protected components can access. In another embodiment, an integrity protected communication broker exchanges data from a communication page of one component to another communication page of another component.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Ravi Sahita, Uday Savagaonkar, Subhash Gutti
  • Publication number: 20090172330
    Abstract: In one embodiment, the present invention includes a virtual machine monitor (VMM) to access a protection indicator of a page table entry (PTE) of a page of a set of memory buffers and determine a state of the protection indicator, and if the protection indicator indicates that the page is a user-level page and if certain information of an agent that seeks to use the page matches that in a protected memory address array, a page table base register (PTBR) is updated to a protected page table (PPT) base address. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Prashant Dewan, Uday Savagaonkar
  • Publication number: 20090119510
    Abstract: End-to-end security between clients and a server, and traffic visibility to intermediate network devices, achieved through combined mode, single pass encryption and authentication using two keys is disclosed. In various embodiments, a combined encryption-authentication unit includes a cipher unit and an authentication unit coupled in parallel to the cipher unit, and generates an authentication tag using an authentication key in parallel with the generation of the cipher text using an encryption key, where the authentication and encryption key have different key values.
    Type: Application
    Filed: November 6, 2007
    Publication date: May 7, 2009
    Inventors: Men Long, Jesse Walker, David Durham, Marc Millier, Karanvir Grewal, Prashant Dewan, Uday Savagaonkar, Steven D. Williams
  • Patent number: 7512768
    Abstract: In one embodiment, the present invention includes a method for receiving a request from a caller code portion of a first color to color at least a portion of a stack with a second color, determining if the request is valid, and if so remapping the stack portion from a first mapping colored with the first color to a second mapping colored with the second color. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: Subhash Gutti, Uday Savagaonkar, Ravi Sahita, David Durham
  • Publication number: 20090006714
    Abstract: In a virtualized processor based system causing a transition to a virtual machine monitor executing on the processor based system in response to a modification of a page table of a guest executing in a virtual machine of the processor based system, and the virtual machine monitor responding to the transition by performing a verification action, and for each bit modified in the page table of the guest, reading a status indicator for the bit to determine if the bit is significant; and causing the transition only if the status indicator for any bit modified in the page table indicates that the bit is significant.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: David Durham, Hormuzd Khosravi, Gayathri Nagabhushan, Uday Savagaonkar
  • Patent number: 7467285
    Abstract: Provided are a method, system, program and device for maintaining shadow page tables in a sequestered memory region. A first processor executing an application invokes a second processor to create a shadow page table used for address translation for the application in a sequestered memory region non-alterable by processes controlled by an operating system executed by the first processor. The shadow page table references at least one page in an operating system memory region accessible to processes controlled by the operating system.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Hormuzd M. Khosravi, Uday Savagaonkar, Ravi Sahita, Priya Rajagopal
  • Publication number: 20080280593
    Abstract: Disclosed is a method for restricting access of a first code of a plurality of codes and data of a first function from a second function. Thee method comprises calling the second function by the first function, addresses of the plurality of data may be stored in a stack page and colored in a first color (102). The method comprises performing access control check in a transition page for verifying whether the first function has permission to call the second function (104). Further the method comprises protecting the first code from the second function by coloring the data and/or addresses in a second color (106). Furthermore, the method comprises executing the second function by pushing addresses of the second function on the stack page, the addresses of the second function colored in a third color (108) and unprotecting the first code by coloring the addresses of the first code in the first color (110).
    Type: Application
    Filed: June 28, 2007
    Publication date: November 13, 2008
    Applicant: INTEL CORPORATION
    Inventors: Uday Savagaonkar, David Durham, Ravi Sahita, Subhash Gutti
  • Publication number: 20080282358
    Abstract: Disclosed is a method for restricting access of a first code of a plurality of codes of a first function from a second function. Thee method comprises calling the second function by the first function, addresses of the plurality of codes are stored in a stack page and colored in a first color (102). The method comprises performing access control check in a transition page for verifying whether the first function has permission to call the second function (104). Further the method comprises protecting the first code from the second function by coloring the addresses in a second color (106). Furthermore, the method comprises executing the second function by pushing addresses of the second function on the stack page, the addresses of the second function colored in a third color (108) and unprotecting the first code by coloring the addresses of the first code in the first color (110).
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Applicant: INTEL CORPORATION
    Inventors: Uday Savagaonkar, David Durham, Ravi Sahita, Subhash Gutti
  • Publication number: 20080244572
    Abstract: Systems and methods are described herein that discuss how a computing platform executing a virtualized environment, in one example, can be integrity verified adaptively and on demand. This may occur at initial runtime, as well as during continued operations, and allows the platform user to install software from various vendors without sacrificing the integrity measurement and therefore the trustworthiness of the platform.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Ravi Sahita, Uday Savagaonkar
  • Publication number: 20080244725
    Abstract: According to one example embodiment of the inventive subject matter, there is described herein a method and apparatus for securely and efficiently managing packet buffers between protection domains on an Intra-partitioned system using packet queues and triggers. According to one embodiment described in more detail below, there is provided a method and apparatus for optimally transferring packet data across contexts (protected and unprotected) in a commodity operating system.
    Type: Application
    Filed: March 31, 2007
    Publication date: October 2, 2008
    Inventors: Prashant Dewan, Uday Savagaonkar, Hormuzd M. Khosravi
  • Publication number: 20080244155
    Abstract: Methods and apparatus to protect dynamic memory regions allocated to programming agents are disclosed. An example method to protect a dynamic memory region disclosed herein comprises mapping protected memory regions to a protected page table for address translation associated with a protected agent, updating the protected page table with address information corresponding to the dynamic memory region during a context switch from execution of an unprotected agent to execution of the protected agent when the dynamic memory region was allocated for the unprotected agent prior to the context switch, and accessing the dynamic memory region during execution of the protected agent based on the address information in the protected page table without causing a subsequent context switch.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Kyungwoo Lee, Prashant Dewan, Uday Savagaonkar
  • Publication number: 20080244758
    Abstract: An apparatus to protect one or more hardware devices from unauthorized software access is described herein and comprises, in one embodiment, a virtual machine manager, a memory protection module and an integrity measurement manager. In a further embodiment, a method of providing secure access to one or more hardware devices may include, modifying a page table, verifying the integrity of a device driver, and providing memory protection to the device driver if the device driver is verified.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Ravi Sahita, Hormuzd M. Khosravi, Uday Savagaonkar, David M. Durham
  • Publication number: 20080244573
    Abstract: A virtual machine monitor; and an executive virtual machine to manage page tables in place of the virtual machine monitor are described. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 31, 2007
    Publication date: October 2, 2008
    Inventors: Ravi Sahita, Uday Savagaonkar, Paul Schmitz
  • Publication number: 20080162849
    Abstract: Hardware of a virtualized processor based system detecting a specified type of memory access to an identified region of memory and in response to the detecting generating an interrupt for a virtual machine monitor (VMM) of the virtualized processor based system.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Uday Savagaonkar, Travis T. Schluessler, Hormuzd Khosravi, Ravi Sahita, Gayathri Nagabhushan, David Durham