Patents by Inventor Uk-Rae Cho
Uk-Rae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11437320Abstract: A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.Type: GrantFiled: March 31, 2020Date of Patent: September 6, 2022Inventors: Suk Youn, Chan Ho Lee, Uk Rae Cho, Woo jin Jung, Kyu Won Choi
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Publication number: 20210028109Abstract: A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.Type: ApplicationFiled: March 31, 2020Publication date: January 28, 2021Inventors: Suk Youn, Chan Ho Lee, Uk Rae Cho, Woo jin Jung, Kyu Won Choi
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Patent number: 9537470Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: GrantFiled: August 12, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee Kim, Min-Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae-Seong Lee, Gun-Ok Jung, Uk-Rae Cho
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Patent number: 9318607Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.Type: GrantFiled: May 9, 2014Date of Patent: April 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Woo Seo, Gun-Ok Jung, Min-Su Kim, Sang-Shin Han, Ju-Hyun Kang, Uk-Rae Cho
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Publication number: 20150349756Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee KIM, Min-Su KIM, Ji-Kyum KIM, Emil KAGRAMANYAN, Dae-Seong LEE, Gun-Ok JUNG, Uk-Rae CHO
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Patent number: 9130550Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: GrantFiled: June 4, 2014Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee Kim, Min-Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae-Seong Lee, Gun-Ok Jung, Uk-Rae Cho
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Publication number: 20150014775Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.Type: ApplicationFiled: May 9, 2014Publication date: January 15, 2015Inventors: Jae-Woo SEO, Gun-Ok JUNG, Min-Su KIM, Sang-Shin HAN, Ju-Hyun KANG, Uk-Rae CHO
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Publication number: 20140368246Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: ApplicationFiled: June 4, 2014Publication date: December 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee KIM, Min-Su KIM, Ji-Kyum KIM, Emil KAGRAMANYAN, Dae-Seong LEE, Gun-Ok JUNG, Uk-Rae CHO
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Publication number: 20140184288Abstract: Provided are a semiconductor circuit and method for operating the same. The semiconductor circuit includes a first flip-flop configured to, based on input data synchronized to a first clock, output first output data synchronized to a second clock different from the first clock, and a second flip-flop configured to, based on the first output data, output second output data synchronized to the second clock, wherein the first and the second flip-flops share an inverted second clock and a delayed second clock and output the first and the second output data based thereon, respectively.Type: ApplicationFiled: December 18, 2013Publication date: July 3, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Chung-Hee KIM, Ju-Hyun KANG, Dong-Youb KIM, Min-su KIM, Sun-Gyeum KIM, Uk-Rae CHO, Sang-Shin HAN
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Patent number: 8578227Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.Type: GrantFiled: November 12, 2010Date of Patent: November 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Jae Son, Yong-Jin Yoon, Uk-Rae Cho
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Patent number: 8531208Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.Type: GrantFiled: March 2, 2012Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Gun Ok Jung, Min Su Kim, Uk Rae Cho, Dae Young Moon, Hyoung Wook Lee
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Publication number: 20120223739Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.Type: ApplicationFiled: March 2, 2012Publication date: September 6, 2012Inventors: Gun Ok JUNG, Min Su Kim, Uk Rae Cho, Dae Young Moon, Hyoung Wook Lee
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Publication number: 20110154142Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.Type: ApplicationFiled: November 12, 2010Publication date: June 23, 2011Inventors: Young-Jae SON, Yong-Jin YOON, Uk-Rae CHO
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Patent number: 7924604Abstract: A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and a first and second pull-up transistors formed in a second layer located above the first layer and connected with the first and second pull-down transistors respectively to form an inverter latch. With the construction of a stacked memory cell having a lone pass transistor, cell size is reduced compared to a conventional six-transistor cell, and driving performance of the pass transistor can be improved.Type: GrantFiled: October 27, 2006Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyang-Ja Yang, Uk-Rae Cho
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Patent number: 7825710Abstract: A delay-locked loop (DLL) circuit and a method for generating transmission core clock signals are provided, where the DLL circuit receives an applied external clock signal and generates a transmission core clock signal, the DLL circuit includes a delay circuit unit and a transmission core clock signal generating unit, the delay circuit unit delays the external clock signal through a plurality of delay units configured in a chain type and outputs a plurality of reference clock signals having different phases, the transmission core clock signal generating unit independently selects and controls two reference signals from the plurality of reference clock signals and thus independently generates transmission core clock signals by the number corresponding to ½ times the number of reference clock signals, and the transmission core clock signals have different phases and a period equal to a period of the external clock signal, wherein transmission core clock signals having a precise phase difference are generated inType: GrantFiled: March 9, 2006Date of Patent: November 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Seog Kim, Uk-Rae Cho
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Patent number: 7697314Abstract: A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line.Type: GrantFiled: January 3, 2008Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Seog Kim, Hak-Soo Yu, Uk-Rae Cho
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Patent number: 7656723Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.Type: GrantFiled: December 31, 2008Date of Patent: February 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Seog Kim, Jong-Cheol Lee, Hak-Soo Yu, Uk-Rae Cho
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Patent number: 7616512Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.Type: GrantFiled: December 31, 2008Date of Patent: November 10, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Seog Kim, Jong-Cheol Lee, Hak-Soo Yu, Uk-Rae Cho
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Patent number: 7551013Abstract: A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generatinType: GrantFiled: May 1, 2006Date of Patent: June 23, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Seog Kim, Uk-Rae Cho
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Publication number: 20090154265Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.Type: ApplicationFiled: December 31, 2008Publication date: June 18, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Seog KIM, Jong-Cheol LEE, Hak-Soo YU, Uk-Rae CHO