Patents by Inventor Uksong Kang

Uksong Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210357130
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin CHO, Sungyong SEO, Sun-Young LIM, Uksong KANG, Chankyung KIM, Duckhyun CHANG, JinHyeok CHOI
  • Patent number: 11106363
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin Cho, Sungyong Seo, Sun-Young Lim, Uksong Kang, Chankyung Kim, Duckhyun Chang, JinHyeok Choi
  • Patent number: 11010304
    Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Uksong Kang, Kjersten E. Criss, Rajat Agarwal, John B. Halbert
  • Patent number: 10824499
    Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chaohong Hu, Hongzhong Zheng, Uksong Kang, Zhan Ping
  • Patent number: 10770129
    Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Hussein Alameer, Kjersten Criss, Uksong Kang
  • Patent number: 10755753
    Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Uksong Kang, Christopher E. Cox
  • Patent number: 10599206
    Abstract: Examples include techniques to change a mode of operation for a memory device. Examples include using information stored at a memory array of the memory device to program mode registers at the memory device to change the mode of operation to a first mode of operation that corresponds to a frequency set point associated with dynamic voltage and frequency scaling for a processor coupled with the memory device.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Uksong Kang
  • Patent number: 10482947
    Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Uksong Kang, Nagi Aboulenein
  • Patent number: 10459809
    Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Hussein Alameer, Uksong Kang, Kjersten E. Criss, Rajat Agarwal, Wei Wu, John B. Halbert
  • Publication number: 20190278487
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 12, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin CHO, Sungyong Seo, Sun-Young Lim, Uksong Kang, Chankyung Kim, Duckhyun Chang, JinHyeok Choi
  • Publication number: 20190252009
    Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 15, 2019
    Inventors: Uksong KANG, Christopher E. COX
  • Publication number: 20190244657
    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Inventors: Uksong Kang, Hoiju Chung
  • Patent number: 10311936
    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Uksong Kang, Hoiju Chung
  • Patent number: 10303372
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin Cho, Sungyong Seo, Sun-Young Lim, Uksong Kang, Chankyung Kim, Duckhyun Chang, JinHyeok Choi
  • Patent number: 10269394
    Abstract: Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chankyung Kim, Uksong Kang, Nam Sung Kim
  • Patent number: 10249351
    Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Uksong Kang, Christopher E. Cox
  • Publication number: 20190096472
    Abstract: A method performed by a memory chip is described. The method includes specially requesting additional refreshes for weak storage cells of the memory chip that deplete their charge more rapidly than other storage cells of the memory chip. The additional refreshes are added to a distributed baseline refresh command sequence that is applied to the weak storage cells and the other storage cells. The distributed baseline refresh command sequence has a refresh rate that is determined from charge depletion characteristics of the other storage cells.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Inventors: Uksong KANG, John B. HALBERT
  • Publication number: 20190042449
    Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.
    Type: Application
    Filed: January 9, 2018
    Publication date: February 7, 2019
    Inventors: Uksong KANG, Kjersten E. CRISS, Rajat AGARWAL, John B. HALBERT
  • Publication number: 20190043552
    Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Hussein Alameer, Kjersten Criss, Uksong Kang
  • Publication number: 20190004909
    Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Hussein ALAMEER, Uksong KANG, Kjersten E. CRISS, Rajat AGARWAL, Wei WU, John B. HALBERT