Patents by Inventor Ulrich Weiss

Ulrich Weiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11300038
    Abstract: The invention relates to an engine having prechamber ignition, in particular a gas engine, that comprises a main combustion space in a cylinder of the engine for combusting an air-fuel mixture and a prechamber having an ignition device arranged therein and a fuel injector arranged therein, wherein the prechamber has at least one transfer port that fluidically connects the prechamber to the main combustion space. The engine is characterized in that the fuel injector arranged in the prechamber is the only fuel injector via which fuel can be introduced into the associated main combustion space.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: April 12, 2022
    Assignee: Liebherr Machines Bulle SA
    Inventors: Bouzid Seba, Ulrich Weiss, Bakir Puran, Roberto Andreutti
  • Publication number: 20210372350
    Abstract: The invention relates to a system for supplying a gaseous fuel that comprises a low temperature tank for receiving the fuel in its liquid aggregate state achieved by cooling and comprises a rail that is fluidically connected to at least one injector device for discharging gaseous fuel into a combustion space. The system is characterized in that it has a pressure store that is configured to receive gaseous fuel and that is fluidically connectable to both the low temperature tank and the rail to buffer fuel coming from the low temperature tank and to supply it to the rail.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 2, 2021
    Inventors: Bouzid SEBA, Ulrich WEISS
  • Publication number: 20210332743
    Abstract: The invention relates to an engine having prechamber ignition, in particular a gas engine, that comprises a main combustion space in a cylinder of the engine for combusting an air-fuel mixture and a prechamber having an ignition device arranged therein and a fuel injector arranged therein, wherein the prechamber has at least one transfer port that fluidically connects the prechamber to the main combustion space. The engine is characterized in that the fuel injector arranged in the prechamber is the only fuel injector via which fuel can be introduced into the associated main combustion space.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 28, 2021
    Inventors: Bouzid Seba, Ulrich Weiss, Bakir Puran, Roberto Andreutti
  • Publication number: 20210301775
    Abstract: The invention relates to a device for supplying a gaseous fuel to an engine that comprises a gas accumulator for receiving highly pressurized gaseous fuel, a gas buffer for receiving medium pressurized gaseous fuel, a gas supply device for delivering a gaseous fuel into an engine combustion space, a first gas line that connects the gas accumulator to the gas buffer and whose gas flow can be regulated via a first valve, a second gas line that connects the gas accumulator to the gas buffer and whose gas flow can be regulated via a second valve, and a third gas line that connects the gas buffer to the gas supply device. The device is further characterized in that a compressor is arranged in the second gas line to increase a pressure of a gaseous fuel flowing from the gas accumulator to the gas buffer.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 30, 2021
    Inventors: Bakir PURAN, Bouzid SEBA, Ulrich WEISS
  • Patent number: 10604229
    Abstract: A mono-rail crane system (and a corresponding operation method) for use in an aircraft. The crane system comprises a first longitudinal mono-rail installable on the underside of a rear cargo door of the airplane parallel to the longitudinal axis of the rear cargo door; a second longitudinal mono-rail, which is installable on a cargo hold ceiling of the aircraft, and, in the fully opened state of the rear cargo door, in aligned continuity with the first longitudinal mono-rail so that the longitudinal axes of the first and second longitudinal mono-rails coincide to form one common longitudinal axis; a crane mobile equipment configured to be moved along the first and second longitudinal mono-rails in order to hoist and transfer the load; and a linear actuator configured to advance and retreat the second longitudinal monorail towards and away from the first longitudinal monorail.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 31, 2020
    Assignees: AIRBUS DEFENCE AND SPACE S.A., AIRBUS DEFENCE AND SPACE GMBH
    Inventors: Ana Rubio Lopez, Daniel Llanes Arias, Oscar Martinez, Ali Lohmann, Ulrich Weiss
  • Publication number: 20170349263
    Abstract: A mono-rail crane system (and a corresponding operation method) for use in an aircraft. The crane system comprises a first longitudinal mono-rail installable on the underside of a rear cargo door of the airplane parallel to the longitudinal axis of the rear cargo door; a second longitudinal mono-rail, which is installable on a cargo hold ceiling of the aircraft, and, in the fully opened state of the rear cargo door, in aligned continuity with the first longitudinal mono-rail so that the longitudinal axes of the first and second longitudinal mono-rails coincide to form one common longitudinal axis; a crane mobile equipment configured to be moved along the first and second longitudinal mono-rails in order to hoist and transfer the load; and a linear actuator configured to advance and retreat the second longitudinal monorail towards and away from the first longitudinal monorail.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 7, 2017
    Inventors: Ana Rubio LOPEZ, Daniel Llanes ARIAS, Oscar MARTINEZ, Ali Lohmann, Ulrich WEISS
  • Publication number: 20170028934
    Abstract: The invention relates to a method having the steps: determining whether a mobile device is inserted into a receptacle slot of a motor vehicle component; after the mobile device is inserted into the receptacle slot, controlling a drive unit to move the mobile device into a stowed position; after a predetermined condition of the vehicle has been detected controlling the drive unit to move the mobile device from the stowed position into a removal position in which the mobile device protrudes farther out of the receptacle slot than it does in the stowage position. The invention also relates to a holding fixture for at least one mobile device as well as a motor vehicle having a holding fixture.
    Type: Application
    Filed: October 17, 2015
    Publication date: February 2, 2017
    Applicant: Audi AG
    Inventors: Jacques HÉLOT, Ulrich WEIß, Immo REDEKER
  • Patent number: 8898503
    Abstract: Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Daniel M. Dreps, Frank D. Ferraiolo, Hubert Harrer, Pak-kin Mak, Ching-Lung L. Tong, Tobias Webel, Ulrich Weiss
  • Patent number: 8868960
    Abstract: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tobias Bergmann, Ralf Ludewig, Tobias Webel, Ulrich Weiss
  • Publication number: 20140136737
    Abstract: Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel M. Dreps, Frank D. Ferraiolo, Hubert Harrer, Pak-kin Mak, Ching-Lung L. Tong, Tobias Webel, Ulrich Weiss
  • Patent number: 8332787
    Abstract: A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Friedhelm Kessler, Thomas M. Makowski, Harald Mielich, Ulrich Weiss
  • Publication number: 20120117524
    Abstract: A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Applicant: International Business Machines Corporation
    Inventors: Friedhelm Kessler, Thomas M. Makowski, Harald Mielich, Ulrich Weiss
  • Publication number: 20120005516
    Abstract: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tobias BERGMANN, Ralf LUDEWIG, Tobias WEBEL, Ulrich WEISS
  • Patent number: 8086657
    Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss
  • Patent number: 7865758
    Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
  • Patent number: 7761726
    Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
  • Patent number: 7667504
    Abstract: The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Florian Braun, Dedric Lichtenau, Thomas Pflueger, Ulrich Weiss
  • Patent number: 7487377
    Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Scott Barnett Swaney, Kenneth Lundy Ward, Tobias Webel, Ulrich Weiss, Matthias Woehrle
  • Publication number: 20090021288
    Abstract: The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.
    Type: Application
    Filed: March 11, 2008
    Publication date: January 22, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Florian Braun, Cedric Lichtenau, Thomas Pflueger, Ulrich Weiss
  • Publication number: 20080294706
    Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
    Type: Application
    Filed: April 9, 2008
    Publication date: November 27, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wilhelm Haller, Rolf Sautter, Christoph Wandel, Ulrich Weiss