Abstract: The present invention relates to computer processors. In particular it relates to a method and respective system for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage. In order to reduce power consumption of adders and concurrently increasing adder speed it is proposed to implement a mixture of static and dynamic logic in the carry network of a 4-bit adder, and to feed output from the first stage directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Abstract: A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

Abstract: Described is a novel implementation of a medium and high frequency on-module (off-chip)/on-chip power noise filter for power noise sensitive circuits. To achieve this, a second order low-pass approach is used. The first stage capacitor is located on-module (off-chip), and the second stage capacitor is implemented on-chip.

Abstract: An electrical circuit for generating clock pulses for a multi-chip computer system which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clock splitter circuit is provided on the clock generation circuit. This clock splitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clock splitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clock splitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.

Abstract: A regulator includes a switching transformer (TR) whose primary winding is divided into two halves through which current flows alternatingly via one respective switching transistor (Q1, Q2). The pulses on the secondary side of the transformer are rectified to attain the output voltage. The output voltage is controlled by pulse width modulated driver pulses for the two switching transistors. A protective circuit (12) with immediate effect terminates the currently applied driver pulse when the current flowing through the conductive switching transistor reaches a critical current value. A protective circuit (14) with delay effect prevents the generation of further driver pulses upon a further increased overload, this prevention being limited with respect to time. The protective system directly is controlled by the primary current of the power regulator.

Abstract: Metal billets trapped in the billet container of an indirect extrusion press are removed by indirect extrusion in the reverse direction until the billet size is reduced sufficiently for the residue to be expelled bodily from the container. The stem used to support the container-closing plug constitutes, or is replaced by a stem for effecting the reverse indirect extrusion.

Abstract: Tricyclic aromatic compounds of the formula ##STR1## including those wherein: (A) R.sub.1 is H, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(b) R.sub.1 is acetyl, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(c) R.sub.1 and R.sub.3 are methyl and R.sub.2 is carbomethoxy;(d) R.sub.1, R.sub.2, and R.sub.3 are hydrogen; and(e) R.sub.1 and R.sub.3 are methyl and R.sub.2 is hydrogenAre intermediates for the total synthesis of steroids.

Abstract: Tricyclic aromatic compounds of the formula ##STR1## including those wherein: (A) R.sub.1 is H, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(b) R.sub.1 is acetyl, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(c) R.sub.1 and R.sub.3 are methyl and R.sub.2 is carbomethoxy;(d) R.sub.1, R.sub.2, and R.sub.3 are hydrogen; and(e) R.sub.1 and R.sub.3 are methyl and R.sub.2 is hydrogenAre intermediates for the total synthesis of steroids.

Abstract: Tricyclic aromatic compounds of the formula ##STR1## including those wherein: A. R.sub.1 is H, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;B. R.sub.1 is acetyl, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;C. R.sub.1 and R.sub.3 are methyl and R.sub.2 is carbomethoxy;D. R.sub.1, R.sub.2, and R.sub.3 are hydrogen; andE. R.sub.1 and R.sub.3 are methyl and R.sub.2 is hydrogenAre intermediates for the total synthesis of steroids.