Abstract: An apparatus includes a memory, a Memory Section Attribute Storage (MSAS) and a memory access circuit (MAC). The memory includes a plurality of memory sections. The MSAS includes one or more entries, wherein at least some of the entries specify, for respective sections of the memory, respective section security policies, respective section base addresses and respective section sizes. The MAC is configured to receive, from a host, a memory access request that specifies an address to be accessed in the memory, to identify a target memory section that corresponds to the address, responsively to the section base addresses and to the section sizes specified in the MSAS, to receive, from the MSAS, a security policy that corresponds to the target memory section, and to apply the security policy to the memory access request.

Abstract: A memory device includes a Non-Volatile Memory (NVM) comprising a plurality of sectors, and a memory access circuit. The memory access circuit is configured to receive, from a host, a logical address of a block of data, to compute a mapping of the logical address to a data physical address comprising a selected sector among the plurality of sectors and a selected data offset within the same selected sector, to compute a metadata physical address that comprises the selected sector and a metadata offset in the selected sector, and to access the block of data at the data physical address, and the metadata at the metadata physical address.

Abstract: A memory device includes a non-volatile memory (NVM) and a secure-programming circuit (SPC). The SPC is configured to receive a program-NVM instruction to program a given data word in a given location of the NVM, and, responsively to receiving the program-NVM instruction, to program bits of the given data word in the NVM in a random order.

Abstract: An apparatus includes a memory, a Memory Section Attribute Storage (MSAS) and a memory access circuit (MAC). The memory includes a plurality of memory sections. The MSAS includes one or more entries, wherein at least some of the entries specify, for respective sections of the memory, respective section security policies, respective section base addresses and respective section sizes. The MAC is configured to receive, from a host, a memory access request that specifies an address to be accessed in the memory, to identify a target memory section that corresponds to the address, responsively to the section base addresses and to the section sizes specified in the MSAS, to receive, from the MSAS, a security policy that corresponds to the target memory section, and to apply the security policy to the memory access request.

Abstract: A memory device includes a Non-Volatile Memory (NVM) comprising a plurality of sectors, and a memory access circuit. The memory access circuit is configured to receive, from a host, a logical address of a block of data, to compute a mapping of the logical address to a data physical address comprising a selected sector among the plurality of sectors and a selected data offset within the same selected sector, to compute a metadata physical address that comprises the selected sector and a metadata offset in the selected sector, and to access the block of data at the data physical address, and the metadata at the metadata physical address.

Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.

Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.

Abstract: A memory device includes a non-volatile memory (NVM) and a secure-programming circuit (SPC). The SPC is configured to receive a program-NVM instruction to program a given data word in a given location of the NVM, and, responsively to receiving the program-NVM instruction, to program bits of the given data word in the NVM in a random order.

Abstract: A method is provided for generating a new instance of an N-bit cryptographic key for storage in a non-volatile memory (NVM) in which unprogrammed cells have a particular binary value. The method includes generating a random N-bit updating sequence, and generating the new instance of the N-bit cryptographic key by negating each bit in a current instance of the N-bit cryptographic key that has the particular binary value and differs from a correspondingly-positioned bit in the random N-bit updating sequence, without negating any bits in the current instance of the N-bit cryptographic key that do not have the particular binary value. Other embodiments are also described.

Abstract: A method is provided for generating a new instance of an N-bit cryptographic key for storage in a non-volatile memory (NVM) in which unprogrammed cells have a particular binary value. The method includes generating a random N-bit updating sequence, and generating the new instance of the N-bit cryptographic key by negating each bit in a current instance of the N-bit cryptographic key that has the particular binary value and differs from a correspondingly-positioned bit in the random N-bit updating sequence, without negating any bits in the current instance of the N-bit cryptographic key that do not have the particular binary value. Other embodiments are also described.

Abstract: A method of controlling access to a flash memory device having multiple sectors divided into multiple blocks of memory, including accepting a virtual block address, calculating a set of possible sectors that can be used for storing data having the virtual block address based on a predefined function, reading meta-data of each sector from the set of possible sectors, wherein the meta-data of a sector includes information for each block in the sector indicating if the block is currently in use and the virtual block address of the data stored in the block, determining the physical block address of the virtual block address if the data is currently stored in a block in the possible sectors or if a block is currently allocated to store the data, wherein the set of possible sectors is distinct for each virtual block address.

Abstract: A non-modular multiplier, a method for non-modular multiplication and a computational device are provided. The non-modular multiplier includes an interface and circuitry. The interface is configured to receive n-bit integers A and B. The circuitry is configured to calculate a non-modular product (A*B) by performing a sequence of computations, and to randomize a pattern of an electrical power consumed by the multiplier when performing the sequence. The sequence includes: generating a random number w, determining moduli M1 and M2 that depend on a number R=2k, k equals a bit-length of M1 and M2, and on the random number w, and calculating a first modular product C=A*B % M1 and a second modular product D=A*B % M2, and producing and outputting the non-modular product (A*B) based on the first and second modular products.

Abstract: In Elliptic Curve Cryptography (ECC), one performs a great number of modular multiplications. These are usually done by Montgomery Multiplication algorithm, which needs the operands to be preprocessed (namely, converted to the Montgomery Domain), which is normally done by an equivalent of a long division. We provide a method to perform this conversion by a single Montgomery multiplication on the raw data. The method is formulated for elliptic curve points represented in Jacobian coordinates but can be extended to other representations.

Abstract: An apparatus includes a processor and a bus encryption unit. The processor is configured to communicate information over a secured data bus, and to communicate respective addresses over an address bus. The bus encryption unit is configured to generate an encryption key based on multiple addresses that appeared on the address bus, and to encrypt the information communicated between the processor and the secured data bus with the encryption key.

Abstract: A method of controlling access to a flash memory device having multiple sectors divided into multiple blocks of memory, including accepting a virtual block address, calculating a set of possible sectors that can be used for storing data having the virtual block address based on a predefined function, reading meta-data of each sector from the set of possible sectors, wherein the meta-data of a sector includes information for each block in the sector indicating if the block is currently in use and the virtual block address of the data stored in the block, determining the physical block address of the virtual block address if the data is currently stored in a block in the possible sectors or if a block is currently allocated to store the data, wherein the set of possible sectors is distinct for each virtual block address.

Abstract: A system, comprising a logic circuit and delay circuitry, is described. The logic circuit is configured to perform a plurality of instances of a particular computation that is based on a plurality of inputs. The delay circuitry is configured to vary a power-consumption profile of the logic circuit over the plurality of instances, by applying, to the inputs, respective delays that vary over the instances, at least some of the delays varying independently from each other. Other embodiments are also described.

Abstract: According to the present disclosure is provided a device and method for mapping management in a flash memory based on partitioning the memory to a main address space and a substitute space, each partition comprising locations in the memory that are denoted by at least three statues according to which locations are mapped from the main space to the substitute space while responsively modifying the statuses.

Abstract: According to the present disclosure is provided a device and method for mapping management in a flash memory based on partitioning the memory to a main address space and a substitute space, each partition comprising locations in the memory that are denoted by at least three statues according to which locations are mapped from the main space to the substitute space while responsively modifying the statuses.

Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.

Abstract: A non-modular multiplier, a method for non-modular multiplication and a computational device are provided. The non-modular multiplier includes an interface and circuitry. The interface is configured to receive n-bit integers A and B. The circuitry is configured to calculate a non-modular product (A*B) by performing a sequence of computations, and to randomize a pattern of an electrical power consumed by the multiplier when performing the sequence. The sequence includes: generating a random number w, determining moduli M1 and M2 that depend on a number R=2k, k equals a bit-length of M1 and M2, and on the random number w, and calculating a first modular product C=A*B % M1 and a second modular product D=A*B % M2, and producing and outputting the non-modular product (A*B) based on the first and second modular products.