Patents by Inventor Utkarsh Y. Kakaiya

Utkarsh Y. Kakaiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210004338
    Abstract: Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Pratik Marolia, Sanjay Kumar, Rajesh Sankaran, Utkarsh Y. Kakaiya
  • Publication number: 20200327256
    Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: INTEL CORPORATION
    Inventors: JOSHUA FENDER, UTKARSH Y. KAKAIYA, MOHAN NAIR, BRIAN MORRIS, PRATIK MAROLIA
  • Publication number: 20200319913
    Abstract: In one embodiment, an apparatus includes an input/output virtualization (IOV) device comprising: at least one function circuit to be shared by a plurality of virtual machines (VMs); and a plurality of assignable device interfaces (ADIs) coupled to the at least one function circuit, wherein each of the plurality of ADIs is to be associated with one of the plurality of VMs and comprises a first process address space identifier (PASID) field to store a first PASID to identify a descriptor queue stored in a host address space and a second PASID field to store a second PASID to identify a data buffer located in a VM address space. Other embodiments are described and claimed.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: SANJAY K. KUMAR, RAJESH SANKARAN, UTKARSH Y. KAKAIYA, PRATIK M. MAROLIA
  • Patent number: 10789370
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 29, 2020
    Assignee: INTEL CORPORATION
    Inventors: Mohan K. Nair, Rajesh M. Sankaran, Utkarsh Y. Kakaiya, Zhenfu Chai, David M. Lee, Pratik M. Marolia
  • Patent number: 10762244
    Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Joshua Fender, Utkarsh Y. Kakaiya, Mohan Nair, Brian Morris, Pratik Marolia
  • Publication number: 20200210363
    Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
  • Publication number: 20200174841
    Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.
    Type: Application
    Filed: June 29, 2017
    Publication date: June 4, 2020
    Applicant: Intel Corporation
    Inventors: Pratik M. MAROLIA, Aaron J. GRIER, Henry M. MITCHEL, Joseph GRECCO, Michael C. ADLER, Utkarsh Y. KAKAIYA, Joshua D. FENDER, Sundar NADATHUR, Nagabhushan CHITLUR
  • Publication number: 20200159969
    Abstract: Systems, apparatuses, methods, and computer-readable media are provided for device interface management. A device includes a device interface, a virtual machine (VM) includes a device driver, both to facilitate assignment of the device to the VM, access of the device by the VM, or removal of the device from being assigned to the VM. The VM is managed by a hypervisor of a computing platform coupled to the device by a computer bus. The device interface includes logic in support of a device management protocol to place the device interface in an unlocked state, a locked state to prevent changes to be made to the device interface, or an operational state to enable access to device registers of the device by the VM or direct memory access to memory address spaces of the VM, or an error state. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 21, 2020
    Inventors: Vedvyas Shanbhogue, Utkarsh Y. Kakaiya, Ravi Sahita, Abhishek Basak, Pradeep Pappachan, Erdem Aktas
  • Publication number: 20200117624
    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.
    Type: Application
    Filed: March 31, 2017
    Publication date: April 16, 2020
    Inventors: Sanjay KUMAR, Rajesh M. SANKARAN, Philip R. LANTZ, Utkarsh Y. KAKAIYA, Kun TIAN
  • Patent number: 10541687
    Abstract: A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an image policy; receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces; validate the first configuration interface based on the user policy; validate the first reconfiguration image based on the image policy; and in response to a determination that the first configuration interface and the first reconfiguration image are both valid, reconfigure the reconfigurable circuit using the first reconfiguration image.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Joshua D. Fender
  • Publication number: 20200012530
    Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 9, 2020
    Inventors: Utkarsh Y. KAKAIYA, Rajesh SANKARAN, Sanjay KUMAR, Kun TIAN, Philip LANTZ
  • Patent number: 10521388
    Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
  • Publication number: 20190370050
    Abstract: A processing device comprises an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.
    Type: Application
    Filed: February 22, 2017
    Publication date: December 5, 2019
    Inventors: Sanjay KUMAR, Rajesh M. SANKARAN, Gilbert NEIGER, Philip R. LANTZ, Jason W. BRANDT, Vedvyas SHANBHOGUE, Utkarsh Y. KAKAIYA, Kun TIAN
  • Publication number: 20190361728
    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2017
    Publication date: November 28, 2019
    Applicant: INTEL CORPORATION
    Inventors: SANJAY KUMAR, PHILIP R. LANTZ, KUN TIAN, UTKARSH Y. KAKAIYA, RAJESH M. SANKARAN
  • Publication number: 20190311123
    Abstract: Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution environment. In the trusted I/O mode, the I/O device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. The trusted agent may provide attestation information to the trusted execution environment. The trusted execution environment may verify the configuration data and the attestation information. Other embodiments are described and claimed.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 10, 2019
    Inventors: Reshma Lal, Pradeep M. Pappachan, Luis Kida, Krystof Zmudzinski, Siddhartha Chhabra, Abhishek Basak, Alpa Narendra Trivedi, Anna Trikalinou, David M. Lee, Vedvyas Shanbhogue, Utkarsh Y. Kakaiya
  • Publication number: 20190146943
    Abstract: A method includes receiving at a management component of an FPGA a persona change request and issuing a request by the management component to a reconfigurable PR slot of the FPGA to change a first persona of a first circuit device of the FPGA to a second persona of a second circuit device of the FPGA. The management component, the reconfigurable PR slot, and the first and second circuit devices are configured in the FPGA core. The method includes switching by the reconfigurable PR slot the first persona to the second persona. The method includes issuing a request by the management component, a host re-enumeration of the reconfigurable PR slot, triggering by the host a re-enumeration component a re-enumeration of the reconfigurable PR slot, and exposing by the reconfigurable PR slot the second persona such that the host is reconfigured to recognize the second circuit device.
    Type: Application
    Filed: December 25, 2018
    Publication date: May 16, 2019
    Applicant: Intel Corporation
    Inventors: Joshua David Fender, Utkarsh Y. Kakaiya
  • Publication number: 20190114196
    Abstract: Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Mitu AGGARWAL, Nrupal JANI, Manasi DEVAL, Kiran PATIL, Parthasarathy SARANGAM, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190114195
    Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Nrupal JANI, Manasi DEVAL, Anjali SINGHAI, Parthasarathy SARANGAM, Mitu AGGARWAL, Neerav PARIKH, Alexander H. DUYCK, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190114194
    Abstract: Examples may include a method of instantiating a virtual machine; instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device by receiving input data requesting assigned resources for the virtual device, allocating assigned resources to the virtual device based at least in part on the input data, and mapping a page location in an address space of the shared physical device for a selected one of the assigned resources to a page location in a memory-mapped input/output (MMIO) space of the virtual device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the MMIO space of the virtual device.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Nrupal JANI, Manasi DEVAL, Anjali SINGHAI, Parthasarathy SARANGAM, Mitu AGGARWAL, Neerav PARIKH, Alexander H. DUYCK, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • Publication number: 20190114283
    Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Applicants: Intel Corporation, Intel Corporation
    Inventors: Manasi DEVAL, Nrupal JANI, Anjali SINGHAI, Parthasarathy SARANGAM, Mitu AGGARWAL, Neerav PARIKH, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN