Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips, which includes forming routing structure(s) that facilitate process limiting yield (PLY) testing of test devices. A routing structure includes an array of link-up regions and a set of metal pads surrounding that array. Each link-up region includes two sections, each having two nodes electrically connected to the terminals of a corresponding two-terminal test device. During PLY testing with a probe card, electrical connections between the test devices and the metal pads through the link-up regions allow each test device to be tested individually. Optionally, additional routing structures with the same footprint are formed down the line and stacked one above the other. These additional routing structures are used for PLY testing with the same probe card. Optionally, dummy pads are formed between stacked routing structures to improve robustness. Also disclosed is a semiconductor structure formed according to this method.

Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

Abstract: A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.

Abstract: A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.

Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

Abstract: Integrated circuits that include bi-directional protection diode structures are disclosed. In one example, an integrated circuit includes a test circuit portion for testing the functionality of the integrated circuit during or after fabrication of the integrated circuit. The test circuit portion includes first, second, and third diode structures and a resistor structure. The first and third diode structures are in parallel with one another and in series with the resistor, and the resistor and the first and third diode structures are in series with the second diode structure. The first and third diode structures are configured for current flow in a first direction and the second diode structure is configured for current flow in a second direction that is opposite the first direction.

Abstract: Mask blanks of the invention include an absorber layer, an anti-reflective layer disposed over the absorber layer, and a hard mask layer disposed over the anti-reflective layer. The absorber layer is absorbent at an exposure wavelength and is reflective at an inspection wavelength. The inspection wavelength is greater than or equal to the exposure wavelength. The anti-reflective layer is not reflective at the inspection wavelength. None of the main constituents of the hard mask layer has an atomic number greater than 41. The mask blank may be a reflective EUVL mask blank or a transparent mask blank.

Abstract: A test pattern or set of patterns, a method of evaluating the transfer properties of the pattern, and a method of determining a parameter of a transfer process (e.g., imaging process) making use of the test pattern is provided. With the test pattern, the impact of line edge roughness on a transferred pattern may be analyzed. For example, the test pattern may be based upon a lines/spaces pattern, wherein periodic structures having a well-defined period and amplitude are adjacent to the lines. A photomask is provided with the test pattern and an image of the pattern is obtained. Edges of the image are determined and, therefrom, a set of edge position data are obtained. Edge position data are fitted to a straight line to determine edge position residuals. An amplitude spectrum is calculated dependent upon spatial frequencies to obtain a amplitude/spatial frequency relationship. A ratio of determined maximum is formed.

Abstract: A test pattern or set of patterns, a method of evaluating the transfer properties of the pattern, and a method of determining a parameter of a transfer process (e.g., imaging process) making use of the test pattern is provided. With the test pattern, the impact of line edge roughness on a transferred pattern may be analyzed. For example, the test pattern may be based upon a lines/spaces pattern, wherein periodic structures having a well-defined period and amplitude are adjacent to the lines. A photomask is provided with the test pattern and an image of the pattern is obtained. Edges of the image are determined and, therefrom, a set of edge position data are obtained. Edge position data are fitted to a straight line to determine edge position residuals. An amplitude spectrum is calculated dependent upon spatial frequencies to obtain a amplitude/spatial frequency relationship. A ratio of determined maximum is formed.